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| REJ09B0270-0400 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 SH7046 Group Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7046 Series HD64F7046 HD6437048 HD6437148 Rev. 4.00 Revision Date: Dec 05, 2005 Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 4.00 Dec 05, 2005 page ii of xliv General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 4.00 Dec 05, 2005 page iii of xliv Rev. 4.00 Dec 05, 2005 page iv of xliv Preface The SH7046 Group single-chip RISC (Reduced Instruction Set Computer) microprocessor includes a Renesas-original RISC CPU as its core, and the peripheral functions required to configure a system. Target users: This manual was written for users who will be using the SH7046 Group MicroComputer Unit(MCU) in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of the SH7046 Group MCU to the above users. Refer to the SH-1, SH-2, SH-DSP Programming Manual for a detailed description of the instruction set. Notes on reading this manual: * Product names The following products are covered in this manual. Product Classifications and Abbreviations Basic Classification SH7046 (80-pin version) On-Chip ROM Classification SH7046F SH7048 SH7148 Flash memory version (ROM: 256 kbytes) Mask ROM version (ROM: 128KB) Mask ROM version (ROM: 64 kbytes) Product Code HD64F7046 HD6437048 HD6437148 In this manual, the product abbreviations are used to distinguish products. For example, 80-pin products are collectively referred to as the SH7046, an abbreviation of the basic type's classification code. There are two versions of each: a flash memory version and a mask ROM version. When a description is limited to the flash memory version alone, the character F is added at the end of the abbreviation, such as SH7046F. When a description is limited to the mask ROM version alone, an abbreviation that is determined by the ROM size is used; for example, SH7148 is used to indicate the mask ROM version. Rev. 4.00 Dec 05, 2005 page v of xliv * The typical product The HD64F7046 is taken as the typical product for the descriptions in this manual. Accordingly, when using an HD6437048 or HD6437148 simply replace the HD64F7046 in those references where no differences between products are pointed out with HD6437048 or HD6437148. Where differences are indicated, be aware that each specification applies to the products as indicated. * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the SH-1, SH-2, SH-DSP Programming Manual. * In order to understand the details of a register when the user knows its name Read the index that is the final part of the manual to find the page number of the entry on the register. The addresses, bit names, and initial values of the registers are summarized in Appendix A, On-chip I/O Register. Rules: Register name: The following notation is used for cases when the same or a similar function, e.g. serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) The MSB (most significant bit) is on the left and the LSB (least significant bit) is on the right. Bit order: Related Manuals: The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com SH7046 Group manuals: Manual Title SH7046 Group Hardware Manual SH-1, SH-2, SH-DSP Programming Manual Document No. This manual REJ09B0171-0500O Rev. 4.00 Dec 05, 2005 page vi of xliv Users manuals for development tools: Manual Title C/C++ Compiler, Assembler, Optimized Linkage Editor Users Manual Simulator Debugger (for Windows) Users Manual High-Performance Embedded Workshop Users Manual Document No. REJ10B0152-0101 ADE-702-186 ADE-702-201 Application Notes: Manual Title C/C++ Compiler Package Application Note Document No. REJ05B0463-0300 Rev. 4.00 Dec 05, 2005 page vii of xliv Rev. 4.00 Dec 05, 2005 page viii of xliv Main Revisions in This Edition Item All Page Revision (See Manual for Details) Hitachi Renesas Technology SH7046 Series SH7046 Group Package Code FP-80Q PRQP0080JD-A 1.4 Pin Functions 8 Table amended Type Symbol UBCTRG User break controller (UBC) (flash version only) 4.3.1 Note on Crystal Resonator 49 Description amended ... As the resonator circuit constants will depend on the resonator and the floating capacitance of the mounting circuit, the component value should be determined in consultation with the resonator manufacturer. 5.1.3 Exception Processing Vector Table Table 5.3 Exception Processing Vector Table 56 Table amended Vector Table Address Offset H'00000120-H'00000123 9.6 On-chip 132 Peripheral I/O Register Access Table 9.2 On-chip Peripheral I/O Register Access Table amended On-chip Peripheral Module Connected bus width Access cycle PFC, PORT 16bit 2cyc* 1 10.3.3 Timer I/O Control Register (TIOR) Table 10.24 TIORL_4 (channel 4) 10.3.6 Timer Counter (TCNT) 162 Note amended Note: 2. When the BFB bit in TMDR_4 is set to 1 and TGRC_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 169 Description amended The TCNT counters are initialized to H'0000 by a reset . Rev. 4.00 Dec 05, 2005 page ix of xliv Item 10.4.5 PWM Modes Figure 10.23 Example of PWM Mode Operation (3) Page 195 Revision (See Manual for Details) Figure amended Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty cycle TGRB rewritten Time TIOCA 10.4.8 Complementary PWM Mode Figure 10.34 Complementary PWM Mode Counter Operation 213 Figure amended Counter value TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 TCNTS 10.7.6 Contention between TGR Write and Compare Match Figure 10.73 Contention between TGR Write and Compare Match 248 Figure amended TGR write cycle T1 T2 P Address Write signal Compare match signal TCNT TGR N N TGR write data N+1 M TGR address Rev. 4.00 Dec 05, 2005 page x of xliv Item 10.7.16 Contention between Overflow/Underflow and Counter Clearing Figure 10.83 Contention between Overflow and Counter Clearing Page 258 Revision (See Manual for Details) Figure amended P TCNT input clock TCNT Counter clear signal TGF Disabled H'FFFF H'0000 TCFV 10.7.17 Contention between TCNT Write and Overflow/Underflow Figure 10.84 Contention between TCNT Write and Overflow 259 Figure amended TCNT write cycle T1 T2 P Address Write signal TCNT address TCNT write data TCNT H'FFFF M TCFV flag 10.7.22 Notes on Buffer Operation Settings 10.9.5 Usage Note 260 Newly added 302 Description added 2. To clear bits POE0F, POE1F, POE2F, POE3F, and OSF to 0, read registers ICSR1 and OCSR. Clear bits, which are read as 1, to 0, and write 1 to the other bits in the registers. 11.1 Features 11.3.3 Reset Control/Status Register (RSTCSR) 303 308 Description replaced Description amended RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset signal when TCNT overflows . Rev. 4.00 Dec 05, 2005 page xi of xliv Item 12.3.7 Serial Status Register (SSR) Page 324 to 326 Revision (See Manual for Details) Table amended Bit 7 6 5 4 3 Bit Name TDRE RDRF ORER FER PER Initial Value 1 0 0 0 0 R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Description [Setting conditions] * * * * * 2 TEND 1 R * Power-on reset or software standby mode Power-on reset or software standby mode Power-on reset or software standby mode Power-on reset or software standby mode Power-on reset or software standby mode [Clearing conditions] [Clearing conditions] [Clearing conditions] [Clearing conditions] [Setting conditions] Power-on reset or software standby mode 12.3.9 Bit Rate Register (BRR) Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1) 335 Table amended Operating Frequency P (MHz) Logical Bit Rate (bit/s) 1000000 2500000 4 n 0 -- N 0* -- n -- 0 10 N -- 0* Table 12.6 BRR 336 Settings for Various Bit Rates (Clocked Synchronous Mode) (2) Table amended Operating Frequency P (MHz) Logical Bit Rate (bit/s) 20 n N 5000000 0 0* 12.4.4 SCI initialization (Asynchronous mode) Figure 12.5 Sample SCI Initialization Flowchart 344 Figure amended Set PFC of the external pin used SCK, TxD, RxD Set RIE, TIE, TEIE, and MPIE bits Set TE and RE bits in SCR to 1 [4] [5] < Initialization completion> Rev. 4.00 Dec 05, 2005 page xii of xliv Item 12.6.1 Clock Page 357 Revision (See Manual for Details) Description amended Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed, the clock is fixed high. Only in reception, the serial clock is continued generating until an overrun error is occurred or the RE bit is cleared to 0. To execute reception in one-character units, select an external clock as a clock source. 12.6.2 SCI initialization (Clocked Synchronous mode) Figure 12.15 Sample SCI Initialization Flowchart 358 Figure amended Set PFC of the external pin used SCK, TxD, RxD Set RIE, TIE, and TEIE bits Set TE and RE bits in SCR to 1 [4] [5] 13.3.2 A/D Control/Status Registers 0 to 2 (ADCSR_0 to ADCSR_2) 373 Table amended Bit 7 Bit Name ADF Initial Value 0 R/W R/(W)* Description [Clearing conditions] * * 5 4 ADM1 ADM0 0 0 R/W R/W When 0 is written after reading ADF = 1 When the DTC is activated by an ADI interrupt and ADDR is read with the DISEL bit in DTMR of DTC = 0 10: Setting prohibited 11: Setting prohibited When changing the operating mode, first clear the ADST bit in the A/D control registers (ADCRs) to 0. 13.3.3 A/D Control Registers_0 to 2 (ADCR_0 to ADCR_2) 375 Table amended Bit 4 Bit Name ADST Initial Value 0 R/W R/W Description ... In continuous scan mode, A/D conversion is continuously performed for the selected channels in sequence until this bit is cleared by a software, reset, or in software standby mode or module standby mode. 14.2.2 Compare Match Timer Control/Status Register_0 and 1(CMCSR_0, CMCSR_1) 389 Table amended Bit 7 Bit Name CMF Initial Value 0 R/W R/(W)* Description Compare Match Flag This flag indicates whether or not the CMCNT and CMCOR values have matched. 0: CMCNT and CMCOR values have not matched 1: CMCNT and CMCOR values have matched [Clearing conditions] * * Write 0 to CMF after reading 1 from it When the DTC is activated by an CMI interrupt and data is transferred with the DISEL bit in DTMR of DTC = 0 Rev. 4.00 Dec 05, 2005 page xiii of xliv Item 15.3.2 Timer Control Register (TCNR) Page 402 Revision (See Manual for Details) Description amended The timer control register (TCNR) controls the enabling or disabling of interrupt requests, selects the enabling or disabling of register access, and selects counter operation or halting . 15.4.1 Sample Setting Procedure PWM Output Generation in Operating Modes: 4. PWM Waveform Figure 15.5 Example of PWM Waveform Generation 413 Figure replaced 15.7.2 Notes for MMT 424 Operation Pay Attention to the Notices Below, When a Value is Written into the Timer General Register U (TGRU), Timer General Register V (TGRV), Timer General Register W (TGRW), and in Case of Written into Free Operation Address (*): Writing Operation into 424 Timer Period Data Register (TPDR) and Timer Dead Time Data Register (TDDR) When MMT is Operating: Notes on Halting TCNT Counter Operation 425 Newly added Newly added Newly added Rev. 4.00 Dec 05, 2005 page xiv of xliv Item 15.8.5 Usage Note Page 431 Revision (See Manual for Details) Description amended 1. To set the POE pin as a level-detective pin, a high level signal must be firstly input to the POE pin. 2. To clear bits POE4F, POE5F, and POE6F to 0, read the ICSR2 register. Clear bits, which are read as 1, to 0, and write 1 to the other bits in the register. 16.2 Usage Notes 18.1 Features 448 459 (3) and (4) newly added Description amended * Reprogramming capability -- For details, see section 22, Electrical Characteristics Rev. 4.00 Dec 05, 2005 page xv of xliv Item 18.8.3 Interrupt Handling when Programming/Erasing Flash Memory Figure 18.10 Erase/Erase-Verify Flowchart Page 479 Revision (See Manual for Details) Figure amended Erase start SWE bit 1 Wait (tSSWE) s n1 Set EBR1 and EBR2 Enable WDT ESU bit 1 Wait (tSESU) E bit 1 Wait (tSE) E bit 0 Wait (tCE) ESU bit 0 Wait (tCESU) Disable WDT EV bit 1 Wait (tSEV) Set block start address as verify address *1 *3 H'FF dummy write to verify address Wait (tSEVR) Read verify data *2 No Increment address Verify data = all 1s? Yes No Last address of block? Yes EV bit 0 Wait (tCEV) No *4 All erase block erased? Yes SWE bit 0 Wait (tCSWE) End of erasing Rev. 4.00 Dec 05, 2005 page xvi of xliv Item 18.13 Notes on Flash Memory Programming and Erasing Section 19 Mask ROM Page 483 to 487 490 Revision (See Manual for Details) Newly added Description amended The operating mode is selected using mode-setting pins FWP and MD3 to MD0 as shown in table 3.1. Only the mode 3 is supported in this LSI. The on-chip ROM is allocated to addresses H'00000000 to H'0000FFFF of memory area 0 (SH7148), H'00000000 to H'0001FFFF of memory area 0 (SH7048). 21.3.2 Software Standby Mode Transition to Software Standby Mode: 22.2 DC Characteristics Table 22.2 DC Characteristics 501 Description amended However, the contents of the CPU's internal registers and onchip RAM data are retained as long as the specified voltage is supplied. ... 508 Table amended Item Schmitt trigger input voltage IRQ3 to IRQ0, POE6 to POE0, TCLKA to TCLKD, TIOC0A to TIOC0D, TIOC1A, TIOC1B, TIOC2A, TIOC2B, TIOC3A to TIOC3D, TIOC4A to TIOC4D Symbol VT+ (VIH) VT- (VIL) VT+-VT- Min VCC - 0.5 -0.3 0.4 Table 22.3 Permitted Output Current Values 510 Table amended Item Output low-level permissible current (total) Symbol IOL Max 110 22.3.9 Port Output Enable (POE) Timing Table 22.11 Port Output Enable (POE) Timing 22.4 A/D Converter Characteristics Table 22.14 A/D Converter Characteristics 524 Title amended 527 Table amended Item Non-linear error (reference value) Offset error (reference value) Full-scale error (reference value) Rev. 4.00 Dec 05, 2005 page xvii of xliv Item 22.5 Flash Memory Characteristics Table 22.15 Flash Memory Characteristics Page 528, 529 Revision (See Manual for Details) Table and notes amended Item Reprogramming count Symbol NWEC NWEC Min 100*7 -- Typ Max Unit Times Times Remarks Standard product Wide temperaturerange product 8 10000* -- -- 100 Data retained time tDRP 10*9 -- -- years Notes: 7. All characteristics after rewriting are guaranteed up to this minimum rewriting times (therefore 1 to min. times). 8. Reference value at 25C (A rough rewriting target number to which a rewriting usually functions) 9. Data retention characteristics when rewriting is executed within the specification values including minimum values. A.2 Register Bits 547, 548 Table amended Register Abbreviation TCSR MSTCR1 Bit 7 OVF MSTCR2 MMT_TMDR Bit 6 WT/IT MSTP14 MSTP6 CKS2 Bit 5 TME MSTP13 MSTP5 CKS1 Bit 4 MSTP12 MSTP4 CKS0 Bit 3 MSTP27 MSTP19 OLSN Bit 2 CKS2 MSTP26 MSTP18 OLSP Bit 1 CKS1 MSTP25 MD1 Bit 0 CKS0 MSTP24 MSTP0 MD0 MMT Module WDT Power-down state A.3 Register States in 551 to Each Operating Mode 556 Hardware Standby deleted Table amended and notes added Register Abbreviation TCSR TCNT RSTCSR Power-On Reset Initialized Initialized Initialized/ Held*2 Manual Reset Initialized Initialized Held Software Standby Initialized/ Held*1 Initialized Initialized Module Standby Sleep Held Held Held Module WDT Notes: 1. The bits 7 to 5 (OVF, WT/IT, and TME) in TCSR are initialized and the bits 2 to 0 (CKS2 to CKS0) are retained. 2. RSTCSR is retained in spite of power-on reset by WDT overflow. Appendix B Pin States Table B.1 Pin States Appendix D Package Dimensions Figure D.1 PRQP0080JD-A 560 Package Code amended and figure replaced 557, 558 Table amended Hardware Standby deleted Rev. 4.00 Dec 05, 2005 page xviii of xliv Contents Section 1 Overview............................................................................................................. 1.1 1.2 1.3 1.4 Features ............................................................................................................................. Internal Block Diagram..................................................................................................... Pin Arrangement ............................................................................................................... Pin Functions .................................................................................................................... 1 1 3 4 5 9 9 9 9 11 12 12 13 13 13 14 14 14 17 21 24 24 37 37 Section 2 CPU ...................................................................................................................... 2.1 2.2 Features ............................................................................................................................. Register Configuration...................................................................................................... 2.2.1 General Registers (Rn)......................................................................................... 2.2.2 Control Registers ................................................................................................. 2.2.3 System Registers.................................................................................................. 2.2.4 Initial Values of Registers.................................................................................... Data Formats..................................................................................................................... 2.3.1 Data Format in Registers...................................................................................... 2.3.2 Data Formats in Memory ..................................................................................... 2.3.3 Immediate Data Format ....................................................................................... Instruction Features........................................................................................................... 2.4.1 RISC-Type Instruction Set................................................................................... 2.4.2 Addressing Modes ............................................................................................... 2.4.3 Instruction Format................................................................................................ Instruction Set ................................................................................................................... 2.5.1 Instruction Set by Classification .......................................................................... Processing States............................................................................................................... 2.6.1 State Transitions................................................................................................... 2.3 2.4 2.5 2.6 Section 3 MCU Operating Modes .................................................................................. 39 3.1 3.2 3.3 Selection of Operating Modes........................................................................................... Input/Output Pins .............................................................................................................. Explanation of Operating Modes ...................................................................................... 3.3.1 Mode 0 to Mode 2 (MCU extension mode 0 to 2) ............................................... 3.3.2 Mode 3 (Single chip mode).................................................................................. 3.3.3 Clock Mode.......................................................................................................... Address Map ..................................................................................................................... Initial State of This LSI..................................................................................................... 39 40 41 41 41 41 42 45 3.4 3.5 Section 4 Clock Pulse Generator..................................................................................... 47 4.1 Oscillator........................................................................................................................... 47 Rev. 4.00 Dec 05, 2005 page xix of xliv 4.2 4.3 4.1.1 Connecting a Crystal Resonator........................................................................... 4.1.2 External Clock Input Method............................................................................... Function for Detecting the Oscillator Halt........................................................................ Usage Notes ...................................................................................................................... 4.3.1 Note on Crystal Resonator ................................................................................... 4.3.2 Notes on Board Design ........................................................................................ 47 48 49 49 49 50 Section 5 Exception Processing....................................................................................... 53 5.1 Overview........................................................................................................................... 5.1.1 Types of Exception Processing and Priority ........................................................ 5.1.2 Exception Processing Operations......................................................................... 5.1.3 Exception Processing Vector Table ..................................................................... Resets ................................................................................................................................ 5.2.1 Types of Reset ..................................................................................................... 5.2.2 Power-On Reset ................................................................................................... 5.2.3 Manual Reset ....................................................................................................... Address Errors .................................................................................................................. 5.3.1 The Cause of Address Error Exception................................................................ 5.3.2 Address Error Exception Processing.................................................................... Interrupts ........................................................................................................................... 5.4.1 Interrupt Sources.................................................................................................. 5.4.2 Interrupt Priority Level ........................................................................................ 5.4.3 Interrupt Exception Processing ............................................................................ Exceptions Triggered by Instructions ............................................................................... 5.5.1 Types of Exceptions Triggered by Instructions ................................................... 5.5.2 Trap Instructions .................................................................................................. 5.5.3 Illegal Slot Instructions ........................................................................................ 5.5.4 General Illegal Instructions.................................................................................. Cases when Exception Sources Are Not Accepted ........................................................... 5.6.1 Immediately after a Delayed Branch Instruction ................................................. 5.6.2 Immediately after an Interrupt-Disabled Instruction............................................ Stack Status after Exception Processing Ends .................................................................. Usage Notes ...................................................................................................................... 5.8.1 Value of Stack Pointer (SP) ................................................................................. 5.8.2 Value of Vector Base Register (VBR) ................................................................. 5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing ...... 53 53 54 55 57 57 57 58 59 59 60 60 60 61 61 62 62 62 63 63 64 64 64 65 66 66 66 66 5.2 5.3 5.4 5.5 5.6 5.7 5.8 Section 6 Interrupt Controller (INTC)........................................................................... 67 6.1 6.2 6.3 Features ............................................................................................................................. 67 Input/Output Pins .............................................................................................................. 69 Register Descriptions ........................................................................................................ 69 Rev. 4.00 Dec 05, 2005 page xx of xliv 6.4 6.5 6.6 6.7 6.8 6.3.1 Interrupt Control Register 1 (ICR1)..................................................................... 6.3.2 Interrupt Control Register 2 (ICR2)..................................................................... 6.3.3 IRQ Status Register (ISR).................................................................................... 6.3.4 Interrupt Priority Registers A, D to K (IPRA, IPRD to IPRK) ............................ Interrupt Sources............................................................................................................... 6.4.1 External Interrupts ............................................................................................... 6.4.2 On-Chip Peripheral Module Interrupts ................................................................ 6.4.3 User Break Interrupt ............................................................................................ Interrupt Exception Processing Vectors Table.................................................................. Interrupt Operation............................................................................................................ 6.6.1 Interrupt Sequence ............................................................................................... 6.6.2 Stack after Interrupt Exception Processing .......................................................... Interrupt Response Time................................................................................................... Data Transfer with Interrupt Request Signals ................................................................... 6.8.1 Handling Interrupt Request Signals as Sources for DTC Activating and CPU Interrupt................................................................................................ 6.8.2 Handling Interrupt Request Signals as Source for DTC Activating, but Not CPU Interrupt.......................................................................................... 6.8.3 Handling Interrupt Request Signals as Source for CPU Interrupt but Not DTC Activating....................................................................................... 70 71 73 74 77 77 78 78 79 82 82 85 85 87 88 88 89 Section 7 User Break Controller (UBC) ....................................................................... 91 7.1 7.2 Overview........................................................................................................................... Register Descriptions ........................................................................................................ 7.2.1 User Break Address Register (UBAR) ................................................................ 7.2.2 User Break Address Mask Register (UBAMR) ................................................... 7.2.3 User Break Bus Cycle Register (UBBR) ............................................................. 7.2.4 User Break Control Register (UBCR).................................................................. Operation .......................................................................................................................... 7.3.1 Flow of the User Break Operation ....................................................................... 7.3.2 Break on On-Chip Memory Instruction Fetch Cycle ........................................... 7.3.3 Program Counter (PC) Values Saved................................................................... Examples of Use ............................................................................................................... Usage Notes ...................................................................................................................... 7.5.1 Simultaneous Fetching of Two Instructions ........................................................ 7.5.2 Instruction Fetches at Branches ........................................................................... 7.5.3 Contention between User Break and Exception Processing ................................ 7.5.4 Break at Non-Delay Branch Instruction Jump Destination.................................. 7.5.5 User Break Trigger Output .................................................................................. 7.5.6 Module Standby Mode Setting ............................................................................ 91 93 93 93 94 96 97 97 99 99 100 102 102 102 103 103 103 104 7.3 7.4 7.5 Rev. 4.00 Dec 05, 2005 page xxi of xliv Section 8 Data Transfer Controller (DTC)................................................................... 105 8.1 8.2 Features ............................................................................................................................. Register Descriptions ........................................................................................................ 8.2.1 DTC Mode Register (DTMR).............................................................................. 8.2.2 DTC Source Address Register (DTSAR)............................................................. 8.2.3 DTC Destination Address Register (DTDAR)..................................................... 8.2.4 DTC Initial Address Register (DTIAR) ............................................................... 8.2.5 DTC Transfer Count Register A (DTCRA) ......................................................... 8.2.6 DTC Transfer Count Register B (DTCRB).......................................................... 8.2.7 DTC Enable Registers (DTER)............................................................................ 8.2.8 DTC Control/Status Register (DTCSR)............................................................... 8.2.9 DTC Information Base Register (DTBR) ............................................................ Operation .......................................................................................................................... 8.3.1 Activation Sources ............................................................................................... 8.3.2 Location of Register Information and DTC Vector Table ................................... 8.3.3 DTC Operation .................................................................................................... 8.3.4 Interrupt Source ................................................................................................... 8.3.5 Operation Timing................................................................................................. 8.3.6 DTC Execution State Counts ............................................................................... Procedures for Using DTC................................................................................................ 8.4.1 Activation by Interrupt......................................................................................... 8.4.2 Activation by Software ........................................................................................ 8.4.3 DTC Use Example ............................................................................................... Cautions on Use ................................................................................................................ 8.5.1 Prohibition against DTC Register Access by DTC .............................................. 8.5.2 Module Standby Mode Setting ............................................................................ 8.5.3 On-Chip RAM ..................................................................................................... 105 107 108 110 110 110 110 110 111 112 113 113 113 114 117 123 123 124 125 125 125 126 127 127 127 127 8.3 8.4 8.5 Section 9 Bus State Controller (BSC) ........................................................................... 129 9.1 9.2 9.3 9.4 Features ............................................................................................................................. Input/Output Pin................................................................................................................ Register Configuration...................................................................................................... Register Descriptions ........................................................................................................ 9.4.1 Bus Control Register 1 (BCR1) ........................................................................... 9.4.2 RAM Emulation Register (RAMER)................................................................... Bus Arbitration.................................................................................................................. On-chip Peripheral I/O Register Access ........................................................................... 129 129 129 131 131 131 132 132 9.5 9.6 Section 10 Multi-Function Timer Pulse Unit (MTU) ............................................... 133 10.1 Features ............................................................................................................................. 133 10.2 Input/Output Pins .............................................................................................................. 137 Rev. 4.00 Dec 05, 2005 page xxii of xliv 10.3 Register Descriptions ........................................................................................................ 10.3.1 Timer Control Register (TCR) ............................................................................. 10.3.2 Timer Mode Register (TMDR) ............................................................................ 10.3.3 Timer I/O Control Register (TIOR) ..................................................................... 10.3.4 Timer Interrupt Enable Register (TIER) .............................................................. 10.3.5 Timer Status Register (TSR)................................................................................ 10.3.6 Timer Counter (TCNT)........................................................................................ 10.3.7 Timer General Register (TGR) ............................................................................ 10.3.8 Timer Start Register (TSTR)................................................................................ 10.3.9 Timer Synchro Register (TSYR) ......................................................................... 10.3.10 Timer Output Master Enable Register (TOER) ................................................... 10.3.11 Timer Output Control Register (TOCR) .............................................................. 10.3.12 Timer Gate Control Register (TGCR).................................................................. 10.3.13 Timer Subcounter (TCNTS) ................................................................................ 10.3.14 Timer Dead Time Data Register (TDDR)............................................................ 10.3.15 Timer Period Data Register (TCDR) ................................................................... 10.3.16 Timer Period Buffer Register (TCBR)................................................................. 10.3.17 Bus Master Interface ............................................................................................ 10.4 Operation .......................................................................................................................... 10.4.1 Basic Functions.................................................................................................... 10.4.2 Synchronous Operation........................................................................................ 10.4.3 Buffer Operation .................................................................................................. 10.4.4 Cascaded Operation ............................................................................................. 10.4.5 PWM Modes ........................................................................................................ 10.4.6 Phase Counting Mode .......................................................................................... 10.4.7 Reset-Synchronized PWM Mode......................................................................... 10.4.8 Complementary PWM Mode ............................................................................... 10.5 Interrupts ........................................................................................................................... 10.5.1 Interrupts and Priorities........................................................................................ 10.5.2 DTC Activation.................................................................................................... 10.5.3 A/D Converter Activation.................................................................................... 10.6 Operation Timing.............................................................................................................. 10.6.1 Input/Output Timing ............................................................................................ 10.6.2 Interrupt Signal Timing........................................................................................ 10.7 Usage Notes ...................................................................................................................... 10.7.1 Module Standby Mode Setting ............................................................................ 10.7.2 Input Clock Restrictions ...................................................................................... 10.7.3 Caution on Period Setting .................................................................................... 10.7.4 Contention between TCNT Write and Clear Operations..................................... 10.7.5 Contention between TCNT Write and Increment Operations.............................. 10.7.6 Contention between TGR Write and Compare Match ......................................... 138 140 144 146 164 166 169 169 170 170 172 173 174 176 176 176 177 177 178 178 183 185 189 191 196 203 207 233 233 235 235 236 236 241 245 245 245 246 246 247 248 Rev. 4.00 Dec 05, 2005 page xxiii of xliv 10.7.7 Contention between Buffer Register Write and Compare Match ........................ 10.7.8 Contention between TGR Read and Input Capture.............................................. 10.7.9 Contention between TGR Write and Input Capture............................................. 10.7.10 Contention between Buffer Register Write and Input Capture ............................ 10.7.11 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection ..... 10.7.12 Counter Value during Complementary PWM Mode Stop ................................... 10.7.13 Buffer Operation Setting in Complementary PWM Mode .................................. 10.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag ................. 10.7.15 Overflow Flags in Reset Sync PWM Mode ......................................................... 10.7.16 Contention between Overflow/Underflow and Counter Clearing........................ 10.7.17 Contention between TCNT Write and Overflow/Underflow............................... 10.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronous PWM Mode...................................................................... 10.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous PWM Mode.......................................................................................................... 10.7.20 Interrupts in Module Standby Mode .................................................................... 10.7.21 Simultaneous Input Capture of TCNT_1 and TCNT_2 in Cascade Connection . 10.7.22 Notes on Buffer Operation Settings ..................................................................... 10.8 MTU Output Pin Initialization .......................................................................................... 10.8.1 Operating Modes.................................................................................................. 10.8.2 Reset Start Operation ........................................................................................... 10.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc.................. 10.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, Etc........................................................................................... 10.9 Port Output Enable (POE)................................................................................................. 10.9.1 Features................................................................................................................ 10.9.2 Pin Configuration................................................................................................. 10.9.3 Register Configuration......................................................................................... 10.9.4 Operation ............................................................................................................. 10.9.5 Usage Note........................................................................................................... 249 251 252 253 253 255 255 256 257 258 259 259 260 260 260 260 261 261 261 262 263 293 293 295 295 300 302 Section 11 Watchdog Timer............................................................................................. 303 11.1 Features ............................................................................................................................. 11.2 Input/Output Pin................................................................................................................ 11.3 Register Descriptions ........................................................................................................ 11.3.1 Timer Counter (TCNT)........................................................................................ 11.3.2 Timer Control/Status Register (TCSR) ................................................................ 11.3.3 Reset Control/Status Register (RSTCSR) ............................................................ 11.4 Operation .......................................................................................................................... 11.4.1 Watchdog Timer Mode ........................................................................................ 11.4.2 Interval Timer Mode ............................................................................................ Rev. 4.00 Dec 05, 2005 page xxiv of xliv 303 304 305 305 305 308 309 309 311 11.4.3 Clearing Software Standby Mode ........................................................................ 11.4.4 Timing of Setting the Overflow Flag (OVF) ....................................................... 11.4.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)........................ 11.5 Interrupts ........................................................................................................................... 11.6 Usage Notes ...................................................................................................................... 11.6.1 Notes on Register Access..................................................................................... 11.6.2 TCNT Write and Increment Contention .............................................................. 11.6.3 Changing CKS2 to CKS0 Bit Values................................................................... 11.6.4 Changing between Watchdog Timer/Interval Timer Modes................................ 11.6.5 System Reset by WDTOVF Signal...................................................................... 11.6.6 Internal Reset in Watchdog Timer Mode............................................................. 11.6.7 Manual Reset in Watchdog Timer Mode ............................................................. 11.6.8 Handling of WDTOVF Pin .................................................................................. 311 312 312 313 313 313 315 315 315 316 316 316 316 Section 12 Serial Communication Interface (SCI) .................................................... 317 12.1 Features ............................................................................................................................. 12.2 Input/Output Pins .............................................................................................................. 12.3 Register Descriptions ........................................................................................................ 12.3.1 Receive Shift Register (RSR) .............................................................................. 12.3.2 Receive Data Register (RDR) .............................................................................. 12.3.3 Transmit Shift Register (TSR) ............................................................................. 12.3.4 Transmit Data Register (TDR)............................................................................. 12.3.5 Serial Mode Register (SMR)................................................................................ 12.3.6 Serial Control Register (SCR).............................................................................. 12.3.7 Serial Status Register (SSR) ................................................................................ 12.3.8 Serial Direction Control Register (SDCR)........................................................... 12.3.9 Bit Rate Register (BRR) ...................................................................................... 12.4 Operation in Asynchronous Mode .................................................................................... 12.4.1 Data Transfer Format........................................................................................... 12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode .................................................................................................................... 12.4.3 Clock.................................................................................................................... 12.4.4 SCI initialization (Asynchronous mode).............................................................. 12.4.5 Data transmission (Asynchronous mode) ............................................................ 12.4.6 Serial data reception (Asynchronous mode) ........................................................ 12.5 Multiprocessor Communication Function......................................................................... 12.5.1 Multiprocessor Serial Data Transmission ............................................................ 12.5.2 Multiprocessor Serial Data Reception ................................................................. 12.6 Operation in Clocked Synchronous Mode ........................................................................ 12.6.1 Clock.................................................................................................................... 12.6.2 SCI initialization (Clocked Synchronous mode).................................................. 317 319 319 320 320 320 320 321 322 324 327 327 340 340 342 343 344 345 347 351 352 354 357 357 357 Rev. 4.00 Dec 05, 2005 page xxv of xliv 12.6.3 Serial data transmission (Clocked Synchronous mode) ....................................... 12.6.4 Serial data reception (Clocked Synchronous mode) ............................................ 12.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous mode).............................................................................. 12.7 SCI Interrupts.................................................................................................................... 12.7.1 Interrupts in Normal Serial Communication Interface Mode .............................. 12.8 Usage Notes ...................................................................................................................... 12.8.1 TDR Write and TDRE Flag ................................................................................. 12.8.2 Module Standby Mode Setting ............................................................................ 12.8.3 Break Detection and Processing (Asynchronous Mode Only)............................. 12.8.4 Sending a Break Signal (Asynchronous Mode Only) .......................................... 12.8.5 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) .................................................................... 12.8.6 Constraints on DTC Use ...................................................................................... 12.8.7 Cautions on Clocked Synchronous External Clock Mode ................................... 12.8.8 Caution on Clocked Synchronous Internal Clock Mode...................................... 358 361 363 365 365 366 366 366 366 366 367 367 367 367 Section 13 A/D Converter................................................................................................. 369 13.1 Features ............................................................................................................................. 13.2 Input/Output Pins .............................................................................................................. 13.3 Register Description.......................................................................................................... 13.3.1 A/D Data Registers 8 to 19 (ADDR8 to ADDR19) ............................................. 13.3.2 A/D Control/Status Registers 0 to 2 (ADCSR_0 to ADCSR_2).......................... 13.3.3 A/D Control Registers_0 to 2 (ADCR_0 to ADCR_2)........................................ 13.3.4 A/D Trigger Select Register (ADTSR) ................................................................ 13.4 Operation .......................................................................................................................... 13.4.1 Single Mode......................................................................................................... 13.4.2 Continuous Scan Mode ........................................................................................ 13.4.3 Single-Cycle Scan Mode...................................................................................... 13.4.4 Input Sampling and A/D Conversion Time ......................................................... 13.4.5 A/D Converter Activation by MTU or MMT ...................................................... 13.4.6 External Trigger Input Timing............................................................................. 13.5 Interrupt Sources and DTC Transfer Requests.................................................................. 13.6 Definitions of A/D Conversion Accuracy......................................................................... 13.7 Usage Notes ...................................................................................................................... 13.7.1 Module Standby Mode Setting ............................................................................ 13.7.2 Permissible Signal Source Impedance ................................................................. 13.7.3 Influences on Absolute Accuracy ........................................................................ 13.7.4 Range of Analog Power Supply and Other Pin Settings ...................................... 13.7.5 Notes on Board Design ........................................................................................ 13.7.6 Notes on Noise Countermeasures ........................................................................ Rev. 4.00 Dec 05, 2005 page xxvi of xliv 369 371 372 372 373 374 376 377 377 378 378 379 380 380 381 382 384 384 384 384 385 385 385 Section 14 Compare Match Timer (CMT)................................................................... 387 14.1 Features ............................................................................................................................. 14.2 Register Descriptions ........................................................................................................ 14.2.1 Compare Match Timer Start Register (CMSTR) ................................................. 14.2.2 Compare Match Timer Control/Status Register_0 and 1 (CMCSR_0, CMCSR_1) ..................................................................................... 14.2.3 Compare Match Timer Counter_0 and 1 (CMCNT_0, CMCNT_1).................... 14.2.4 Compare Match Timer Constant Register_0 and 1 (CMCOR_0, CMCOR_1).... 14.3 Operation .......................................................................................................................... 14.3.1 Cyclic Count Operation ....................................................................................... 14.3.2 CMCNT Count Timing........................................................................................ 14.4 Interrupts ........................................................................................................................... 14.4.1 Interrupt Sources.................................................................................................. 14.4.2 Compare Match Flag Set Timing......................................................................... 14.4.3 Compare Match Flag Clear Timing ..................................................................... 14.5 Usage Notes ...................................................................................................................... 14.5.1 Contention between CMCNT Write and Compare Match................................... 14.5.2 Contention between CMCNT Word Write and Incrementation .......................... 14.5.3 Contention between CMCNT Byte Write and Incrementation ............................ 387 388 388 389 390 390 391 391 391 392 392 392 393 393 393 394 395 Section 15 Motor Management Timer (MMT)........................................................... 397 15.1 Features ............................................................................................................................. 15.2 Input/Output Pins .............................................................................................................. 15.3 Register Descriptions ........................................................................................................ 15.3.1 Timer Mode Register (MMT_TMDR)................................................................. 15.3.2 Timer Control Register (TCNR) .......................................................................... 15.3.3 Timer Status Register (MMT_TSR) .................................................................... 15.3.4 Timer Counter (MMT_TCNT) ............................................................................ 15.3.5 Timer Buffer Registers (TBR) ............................................................................. 15.3.6 Timer General Registers (TGR)........................................................................... 15.3.7 Timer Dead Time Counters (TDCNT)................................................................. 15.3.8 Timer Dead Time Data Register (MMT_TDDR) ................................................ 15.3.9 Timer Period Buffer Register (TPBR) ................................................................. 15.3.10 Timer Period Data Register (TPDR).................................................................... 15.4 Operation .......................................................................................................................... 15.4.1 Sample Setting Procedure .................................................................................... 15.4.2 Output Protection Functions ................................................................................ 15.5 Interrupts ........................................................................................................................... 15.6 Operation Timing.............................................................................................................. 15.6.1 Input/Output Timing ............................................................................................ 15.6.2 Interrupt Signal Timing........................................................................................ 397 399 400 401 402 404 405 405 405 405 405 406 406 406 407 416 416 417 417 420 Rev. 4.00 Dec 05, 2005 page xxvii of xliv 15.7 Usage Notes ...................................................................................................................... 15.7.1 Module Standby Mode Setting ............................................................................ 15.7.2 Notes for MMT Operation ................................................................................... 15.8 Port Output Enable (POE)................................................................................................. 15.8.1 Features................................................................................................................ 15.8.2 Input/Output Pins ................................................................................................. 15.8.3 Register Description............................................................................................. 15.8.4 Operation ............................................................................................................. 15.8.5 Usage Note........................................................................................................... 422 422 422 426 426 427 427 430 431 433 438 439 439 442 443 444 445 448 Section 16 Pin Function Controller (PFC) ................................................................... 16.1 Register Descriptions ........................................................................................................ 16.1.1 Port A I/O Register L (PAIORL) ......................................................................... 16.1.2 Port A Control Registers L3 to L1 (PACRL3 to PACRL1)................................. 16.1.3 Port B I/O Register (PBIOR) ............................................................................... 16.1.4 Port B Control Registers 1 and 2 (PBCR1 and PBCR2)...................................... 16.1.5 Port E I/O Registers L and H (PEIORL and PEIORH)........................................ 16.1.6 Port E Control Registers L1, L2, and H (PECRL1, PECRL2, and PECRH) ....... 16.2 Usage Notes ...................................................................................................................... Section 17 I/O Ports............................................................................................................ 449 17.1 Port A................................................................................................................................ 17.1.1 Register Description............................................................................................. 17.1.2 Port A Data Register L (PADRL) ........................................................................ 17.2 Port B ................................................................................................................................ 17.2.1 Register Descriptions ........................................................................................... 17.2.2 Port B Data Register (PBDR) .............................................................................. 17.3 Port E ................................................................................................................................ 17.3.1 Register Descriptions ........................................................................................... 17.3.2 Port E Data Registers H and L (PEDRH and PEDRL) ........................................ 17.4 Port F................................................................................................................................. 17.4.1 Register Description............................................................................................. 17.4.2 Port F Data Register (PFDR) ............................................................................... 17.5 Port G................................................................................................................................ 17.5.1 Register Description............................................................................................. 17.5.2 Port G Data Register (PGDR) .............................................................................. 449 450 450 451 451 452 453 454 454 456 456 456 457 458 458 Section 18 Flash Memory (F-ZTAT Version) ............................................................ 459 18.1 Features ............................................................................................................................. 459 18.2 Mode Transitions .............................................................................................................. 460 18.3 Block Configuration.......................................................................................................... 464 Rev. 4.00 Dec 05, 2005 page xxviii of xliv 18.4 Input/Output Pins .............................................................................................................. 18.5 Register Descriptions ........................................................................................................ 18.5.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 18.5.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 18.5.3 Erase Block Register 1 (EBR1) ........................................................................... 18.5.4 Erase Block Register 2 (EBR2) ........................................................................... 18.5.5 RAM Emulation Register (RAMER)................................................................... 18.6 On-Board Programming Modes........................................................................................ 18.6.1 Boot Mode ........................................................................................................... 18.6.2 Programming/Erasing in User Program Mode..................................................... 18.7 Flash Memory Emulation in RAM ................................................................................... 18.8 Flash Memory Programming/Erasing ............................................................................... 18.8.1 Program/Program-Verify Mode........................................................................... 18.8.2 Erase/Erase-Verify Mode..................................................................................... 18.8.3 Interrupt Handling when Programming/Erasing Flash Memory.......................... 18.9 Program/Erase Protection ................................................................................................. 18.9.1 Hardware Protection ............................................................................................ 18.9.2 Software Protection.............................................................................................. 18.9.3 Error Protection.................................................................................................... 18.10 PROM Programmer Mode ................................................................................................ 18.11 Usage Note........................................................................................................................ 18.12 Notes when Converting the F-ZTAT Versions to the Mask-ROM Versions.................... 18.13 Notes on Flash Memory Programming and Erasing ......................................................... 465 465 465 467 467 468 469 470 471 473 474 476 476 478 478 480 480 480 481 482 482 482 483 Section 19 Mask ROM....................................................................................................... 489 19.1 Usage Note........................................................................................................................ 490 Section 20 RAM .................................................................................................................. 491 20.1 Usage Note........................................................................................................................ 491 Section 21 Power-Down Modes...................................................................................... 493 21.1 Input/Output Pins .............................................................................................................. 21.2 Register Descriptions ........................................................................................................ 21.2.1 Standby Control Register (SBYCR) .................................................................... 21.2.2 System Control Register (SYSCR) ...................................................................... 21.2.3 Module Standby Control Registers 1 and 2 (MSTCR1 and MSTCR2) ............... 21.3 Operation .......................................................................................................................... 21.3.1 Sleep Mode .......................................................................................................... 21.3.2 Software Standby Mode....................................................................................... 21.3.3 Module Standby Mode......................................................................................... 21.4 Usage Notes ...................................................................................................................... 496 496 496 498 499 501 501 501 504 505 Rev. 4.00 Dec 05, 2005 page xxix of xliv 21.4.1 21.4.2 21.4.3 21.4.4 21.4.5 I/O Port Status...................................................................................................... Current Consumption during Oscillation Stabilization Wait Period .................... On-Chip Peripheral Module Interrupt.................................................................. Writing to MSTCR1 and MSTCR2 ..................................................................... DTC Operation in Sleep Mode ............................................................................ 505 505 505 505 505 Section 22 Electrical Characteristics.............................................................................. 507 22.1 Absolute Maximum Ratings ............................................................................................. 22.2 DC Characteristics ............................................................................................................ 22.3 AC Characteristics ............................................................................................................ 22.3.1 Test Conditions for the AC Characteristics.......................................................... 22.3.2 Clock Timing ....................................................................................................... 22.3.3 Control Signal Timing ......................................................................................... 22.3.4 Multi-Function Timer Pulse Unit (MTU)Timing................................................. 22.3.5 I/O Port Timing.................................................................................................... 22.3.6 Watchdog Timer (WDT)Timing.......................................................................... 22.3.7 Serial Communication Interface (SCI)Timing..................................................... 22.3.8 Motor Management Timer (MMT) Timing ......................................................... 22.3.9 Port Output Enable (POE) Timing....................................................................... 22.3.10 A/D Converter Timing......................................................................................... 22.3.11 UBC Trigger Timing............................................................................................ 22.4 A/D Converter Characteristics .......................................................................................... 22.5 Flash Memory Characteristics........................................................................................... 507 508 511 511 512 514 517 519 520 521 523 524 525 526 527 528 Appendix A Internal I/O Register................................................................................... 531 A.1 A.2 A.3 Register Addresses (Order of Address)............................................................................. 531 Register Bits...................................................................................................................... 541 Register States in Each Operating Mode........................................................................... 551 Appendix B Pin States ....................................................................................................... 557 Appendix C Product Code Lineup.................................................................................. 559 Appendix D Package Dimensions .................................................................................. 560 Index .......................................................................................................................................... 561 Rev. 4.00 Dec 05, 2005 page xxx of xliv Figures Section 1 Overview Figure 1.1 Internal Block Diagram of SH7046 ..................................................................... Figure 1.2 SH7046 Pin Arrangement .................................................................................... Section 2 CPU Figure 2.1 CPU Internal Registers......................................................................................... Figure 2.2 Data Format in Registers...................................................................................... Figure 2.3 Data Formats in Memory ..................................................................................... Figure 2.4 Transitions between Processing States................................................................. 3 4 10 13 13 37 Section 3 MCU Operating Modes Figure 3.1 The Address Map of SH7046 Flash Memory Version......................................... 42 Figure 3.2 The Address Map of SH7048 Mask ROM Version ............................................. 43 Figure 3.3 The Address Map of SH7148 Mask ROM Version ............................................. 44 Section 4 Clock Pulse Generator Figure 4.1 Block Diagram of the Clock Pulse Generator...................................................... Figure 4.2 Connection of the Crystal Resonator (Example).................................................. Figure 4.3 Crystal Resonator Equivalent Circuit................................................................... Figure 4.4 Example of External Clock Connection............................................................... Figure 4.5 Cautions for Oscillator Circuit System Board Design ......................................... Figure 4.6 Recommended External Circuitry Around the PLL............................................. Section 6 Interrupt Controller (INTC) Figure 6.1 INTC Block Diagram........................................................................................... Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control ........................................... Figure 6.3 Interrupt Sequence Flowchart .............................................................................. Figure 6.4 Stack after Interrupt Exception Processing .......................................................... Figure 6.5 Example of the Pipeline Operation when an IRQ Interrupt is Accepted ............. Figure 6.6 Interrupt Control Block Diagram ......................................................................... 47 48 48 49 50 50 68 78 84 85 87 88 Section 7 User Break Controller (UBC) Figure 7.1 User Break Controller Block Diagram................................................................. 92 Figure 7.2 Break Condition Determination Method.............................................................. 98 Section 8 Data Transfer Controller (DTC) Figure 8.1 Block Diagram of DTC........................................................................................ 106 Figure 8.2 Activating Source Control Block Diagram .......................................................... 114 Rev. 4.00 Dec 05, 2005 page xxxi of xliv Figure 8.3 Figure 8.4 Figure 8.5 Figure 8.6 Figure 8.7 Figure 8.8 Figure 8.9 Figure 8.10 DTC Register Information Allocation in Memory Space .................................... Correspondence between DTC Vector Address and Transfer Information ......... DTC Operation Flowchart ................................................................................... Memory Mapping in Normal Mode..................................................................... Memory Mapping in Repeat Mode...................................................................... Memory Mapping in Block Transfer Mode ......................................................... Chain Transfer ..................................................................................................... DTC Operation Timing Example (Normal Mode)............................................... 114 115 118 119 120 121 122 123 Section 10 Multi-Function Timer Pulse Unit (MTU) Figure 10.1 Block Diagram of MTU....................................................................................... Figure 10.2 Complementary PWM Mode Output Level Example.......................................... Figure 10.3 Example of Counter Operation Setting Procedure............................................... Figure 10.4 Free-Running Counter Operation......................................................................... Figure 10.5 Periodic Counter Operation ................................................................................. Figure 10.6 Example of Setting Procedure for Waveform Output by Compare Match .......... Figure 10.7 Example of 0 Output/1 Output Operation............................................................ Figure 10.8 Example of Toggle Output Operation.................................................................. Figure 10.9 Example of Input Capture Operation Setting Procedure...................................... Figure 10.10 Example of Input Capture Operation ................................................................... Figure 10.11 Example of Synchronous Operation Setting Procedure ....................................... Figure 10.12 Example of Synchronous Operation .................................................................... Figure 10.13 Compare Match Buffer Operation ....................................................................... Figure 10.14 Input Capture Buffer Operation ........................................................................... Figure 10.15 Example of Buffer Operation Setting Procedure ................................................. Figure 10.16 Example of Buffer Operation (1) ......................................................................... Figure 10.17 Example of Buffer Operation (2) ......................................................................... Figure 10.18 Cascaded Operation Setting Procedure................................................................ Figure 10.19 Example of Cascaded Operation.......................................................................... Figure 10.20 Example of PWM Mode Setting Procedure......................................................... Figure 10.21 Example of PWM Mode Operation (1)................................................................ Figure 10.22 Example of PWM Mode Operation (2)................................................................ Figure 10.23 Example of PWM Mode Operation (3)................................................................ Figure 10.24 Example of Phase Counting Mode Setting Procedure ......................................... Figure 10.25 Example of Phase Counting Mode 1 Operation................................................... Figure 10.26 Example of Phase Counting Mode 2 Operation................................................... Figure 10.27 Example of Phase Counting Mode 3 Operation................................................... Figure 10.28 Example of Phase Counting Mode 4 Operation................................................... Figure 10.29 Phase Counting Mode Application Example ....................................................... Figure 10.30 Procedure for Selecting the Reset-Synchronized PWM Mode ............................ 136 174 178 179 180 180 181 181 182 183 184 185 186 186 187 188 189 190 190 193 194 194 195 196 197 198 199 200 202 205 Rev. 4.00 Dec 05, 2005 page xxxii of xliv Figure 10.31 Reset-Synchronized PWM Mode Operation Example (When the TOCR's OLSN = 1 and OLSP = 1).................................................... Figure 10.32 Block Diagram of Channels 3 and 4 in Complementary PWM Mode................. Figure 10.33 Example of Complementary PWM Mode Setting Procedure .............................. Figure 10.34 Complementary PWM Mode Counter Operation ................................................ Figure 10.35 Example of Complementary PWM Mode Operation........................................... Figure 10.36 Example of PWM Cycle Updating ...................................................................... Figure 10.37 Example of Data Update in Complementary PWM Mode................................... Figure 10.38 Example of Initial Output in Complementary PWM Mode (1) ........................... Figure 10.39 Example of Initial Output in Complementary PWM Mode (2) ........................... Figure 10.40 Example of Complementary PWM Mode Waveform Output (1) ........................ Figure 10.41 Example of Complementary PWM Mode Waveform Output (2) ........................ Figure 10.42 Example of Complementary PWM Mode Waveform Output (3) ........................ Figure 10.43 Example of Complementary PWM Mode 0% and 100% Waveform Output (1). Figure 10.44 Example of Complementary PWM Mode 0% and 100% Waveform Output (2). Figure 10.45 Example of Complementary PWM Mode 0% and 100% Waveform Output (3). Figure 10.46 Example of Complementary PWM Mode 0% and 100% Waveform Output (4). Figure 10.47 Example of Complementary PWM Mode 0% and 100% Waveform Output (5). Figure 10.48 Example of Toggle Output Waveform Synchronized with PWM Output ........... Figure 10.49 Counter Clearing Synchronized with Another Channel....................................... Figure 10.50 Example of Output Phase Switching by External Input (1) ................................. Figure 10.51 Example of Output Phase Switching by External Input (2) ................................. Figure 10.52 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1) Figure 10.53 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) Figure 10.54 Count Timing in Internal Clock Operation .......................................................... Figure 10.55 Count Timing in External Clock Operation ......................................................... Figure 10.56 Count Timing in External Clock Operation (Phase Counting Mode) .................. Figure 10.57 Output Compare Output Timing (Normal Mode/PWM Mode) ........................... Figure 10.58 Output Compare Output Timing (Complementary PWM Mode/ Reset Synchronous PWM Mode)......................................................................... Figure 10.59 Input Capture Input Signal Timing ...................................................................... Figure 10.60 Counter Clear Timing (Compare Match)............................................................. Figure 10.61 Counter Clear Timing (Input Capture)................................................................. Figure 10.62 Buffer Operation Timing (Compare Match) ........................................................ Figure 10.63 Buffer Operation Timing (Input Capture)............................................................ Figure 10.64 TGI Interrupt Timing (Compare Match).............................................................. Figure 10.65 TGI Interrupt Timing (Input Capture).................................................................. Figure 10.66 TCIV Interrupt Setting Timing ............................................................................ Figure 10.67 TCIU Interrupt Setting Timing ............................................................................ Figure 10.68 Timing for Status Flag Clearing by the CPU ....................................................... Figure 10.69 Timing for Status Flag Clearing by DTC Activation ........................................... 206 209 211 213 215 217 219 220 221 223 223 224 224 225 225 226 226 227 228 230 230 231 231 236 236 237 237 238 238 239 239 240 240 241 242 243 243 244 244 Rev. 4.00 Dec 05, 2005 page xxxiii of xliv Figure 10.70 Figure 10.71 Figure 10.72 Figure 10.73 Figure 10.74 Figure 10.75 Figure 10.76 Figure 10.77 Figure 10.78 Figure 10.79 Figure 10.80 Figure 10.81 Figure 10.82 Figure 10.83 Figure 10.84 Figure 10.85 Figure 10.86 Figure 10.87 Figure 10.88 Figure 10.89 Figure 10.90 Figure 10.91 Figure 10.92 Figure 10.93 Figure 10.94 Figure 10.95 Figure 10.96 Figure 10.97 Figure 10.98 Figure 10.99 Figure 10.100 Figure 10.101 Figure 10.102 Figure 10.103 Figure 10.104 Figure 10.105 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode............... Contention between TCNT Write and Clear Operations ..................................... Contention between TCNT Write and Increment Operations.............................. Contention between TGR Write and Compare Match ......................................... Contention between Buffer Register Write and Compare Match (Channel 0)..... Contention between Buffer Register Write and Compare Match (Channels 3 and 4) ............................................................................................... Contention between TGR Read and Input Capture.............................................. Contention between TGR Write and Input Capture............................................. Contention between Buffer Register Write and Input Capture ............................ TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection ........................................................................................................... Counter Value during Complementary PWM Mode Stop ................................... Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode ........... Reset Sync PWM Mode Overflow Flag............................................................... Contention between Overflow and Counter Clearing .......................................... Contention between TCNT Write and Overflow ................................................. Error Occurrence in Normal Mode, Recovery in Normal Mode.......................... Error Occurrence in Normal Mode, Recovery in PWM Mode 1 ......................... Error Occurrence in Normal Mode, Recovery in PWM Mode 2 ......................... Error Occurrence in Normal Mode, Recovery in Phase Counting Mode............. Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode.. Error Occurrence in Normal Mode, Recovery in Reset-Synchronous PWM Mode.......................................................................................................... Error Occurrence in PWM Mode 1, Recovery in Normal Mode ......................... Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1......................... Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2......................... Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode ............ Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode . Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronous PWM Mode.......................................................................................................... Error Occurrence in PWM Mode 2, Recovery in Normal Mode ......................... Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1......................... Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2......................... Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode ............ Error Occurrence in Phase Counting Mode, Recovery in Normal Mode............. Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1 ............ Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2 ............ Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode .................................................................................................... Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode.. 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 Rev. 4.00 Dec 05, 2005 page xxxiv of xliv Figure 10.106 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1 .................................................................................. Figure 10.107 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode........................................................... Figure 10.108 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode........................................................... Figure 10.109 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronous PWM Mode ..................................................... Figure 10.110 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Normal Mode................................................................................... Figure 10.111 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in PWM Mode 1 .................................................................................. Figure 10.112 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Complementary PWM Mode........................................................... Figure 10.113 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Reset-Synchronous PWM Mode ..................................................... Figure 10.114 POE Block Diagram ............................................................................................ Figure 10.115 Low-Level Detection Operation .......................................................................... Figure 10.116 Output-Level Detection Operation....................................................................... Figure 10.117 Falling Edge Detection Operation........................................................................ 285 286 287 288 289 290 291 292 294 300 301 302 Section 11 Watchdog Timer Figure 11.1 Block Diagram of WDT....................................................................................... 304 Figure 11.2 Operation in Watchdog Timer Mode ................................................................... 310 Figure 11.3 Operation in Interval Timer Mode ....................................................................... 311 Figure 11.4 Timing of Setting OVF ........................................................................................ 312 Figure 11.5 Timing of Setting WOVF .................................................................................... 312 Figure 11.6 Writing to TCNT and TCSR................................................................................ 313 Figure 11.7 Writing to RSTCSR ............................................................................................. 314 Figure 11.8 Contention between TCNT Write and Increment ................................................ 315 Figure 11.9 Example of System Reset Circuit Using WDTOVF Signal................................. 316 Section 12 Serial Communication Interface (SCI) Figure 12.1 Block Diagram of SCI ......................................................................................... Figure 12.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits).......................................................................................... Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode..................................... Figure 12.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode) ......................................................................................... Figure 12.5 Sample SCI Initialization Flowchart.................................................................... 318 340 342 343 344 Rev. 4.00 Dec 05, 2005 page xxxv of xliv Figure 12.6 Figure 12.7 Figure 12.8 Figure 12.9 Figure 12.9 Figure 12.10 Figure 12.11 Figure 12.12 Figure 12.13 Figure 12.13 Figure 12.14 Figure 12.15 Figure 12.16 Figure 12.17 Figure 12.18 Figure 12.19 Figure 12.20 Figure 12.21 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)................................................. Sample Serial Transmission Flowchart................................................................ Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) ....................................................................................................... Sample Serial Reception Data Flowchart (1)....................................................... Sample Serial Reception Data Flowchart (2)....................................................... Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) ........................................ Sample Multiprocessor Serial Transmission Flowchart....................................... Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ....................................................................... Sample Multiprocessor Serial Reception Flowchart (1) ...................................... Sample Multiprocessor Serial Reception Flowchart (2) ...................................... Data Format in Clocked Synchronous Communication (For LSB-First)............. Sample SCI Initialization Flowchart.................................................................... Sample SCI Transmission Operation in Clocked Synchronous Mode................. Sample Serial Transmission Flowchart................................................................ Example of SCI Operation in Reception.............................................................. Sample Serial Reception Flowchart ..................................................................... Sample Flowchart of Simultaneous Serial Transmit and Receive Operations..... Example of Clocked Synchronous Transmission with DTC................................ 345 346 347 349 350 352 353 354 355 356 357 358 359 360 361 362 364 367 Section 13 A/D Converter Figure 13.1 Block Diagram of A/D Converter (For One Module).......................................... Figure 13.2 A/D Conversion Timing ...................................................................................... Figure 13.3 External Trigger Input Timing............................................................................. Figure 13.4 Definitions of A/D Conversion Accuracy............................................................ Figure 13.5 Definitions of A/D Conversion Accuracy............................................................ Figure 13.6 Example of Analog Input Circuit......................................................................... Figure 13.7 Example of Analog Input Protection Circuit ....................................................... Figure 13.8 Analog Input Pin Equivalent Circuit.................................................................... 370 379 381 383 383 384 386 386 Section 14 Compare Match Timer (CMT) Figure 14.1 CMT Block Diagram ........................................................................................... 387 Figure 14.2 Counter Operation................................................................................................ 391 Figure 14.3 Count Timing....................................................................................................... 391 Figure 14.4 CMF Set Timing .................................................................................................. 392 Figure 14.5 Timing of CMF Clear by the CPU....................................................................... 393 Figure 14.6 CMCNT Write and Compare Match Contention ................................................. 393 Figure 14.7 CMCNT Word Write and Increment Contention................................................. 394 Rev. 4.00 Dec 05, 2005 page xxxvi of xliv Figure 14.8 CMCNT Byte Write and Increment Contention .................................................. 395 Section 15 Motor Management Timer (MMT) Figure 15.1 Block Diagram of MMT ...................................................................................... Figure 15.2 Sample Operating Mode Setting Procedure......................................................... Figure 15.3 Example of TCNT Count Operation .................................................................... Figure 15.4 Examples of Counter and Register Operations .................................................... Figure 15.5 Example of PWM Waveform Generation............................................................ Figure 15.6 Example of TCNT Counter Clearing ................................................................... Figure 15.7 Example of Toggle Output Waveform Synchronized with PWM Cycle ............. Figure 15.8 Count Timing....................................................................................................... Figure 15.9 TCNT Counter Clearing Timing.......................................................................... Figure 15.10 TDCNT Operation Timing .................................................................................. Figure 15.11 Buffer Operation Timing ..................................................................................... Figure 15.12 TGI Interrupt Timing ........................................................................................... Figure 15.13 Timing of Status Flag Clearing by CPU .............................................................. Figure 15.14 Timing of Status Flag Clearing by DTC Controller............................................. Figure 15.15 Contention between Buffer Register Write and Compare Match ........................ Figure 15.16 Contention between Compare Register Write and Compare Match .................... Figure 15.17 Writing into Timer General Registers (When One Cycle is Not Output) ............ Figure 15.18 Block Diagram of POE ........................................................................................ Figure 15.19 Low Level Detection Operation........................................................................... Section 17 I/O Ports Figure 17.1 Port A................................................................................................................... Figure 17.2 Port B ................................................................................................................... Figure 17.3 Port E ................................................................................................................... Figure 17.4 Port F ................................................................................................................... Figure 17.5 Port G................................................................................................................... Section 18 Flash Memory (F-ZTAT Version) Figure 18.1 Block Diagram of Flash Memory ....................................................................... Figure 18.2 Flash Memory State Transitions .......................................................................... Figure 18.3 Boot Mode ........................................................................................................... Figure 18.4 User Program Mode............................................................................................. Figure 18.5 Flash Memory Block Configuration .................................................................... Figure 18.6 Programming/Erasing Flowchart Example in User Program Mode..................... Figure 18.7 Flowchart for Flash Memory Emulation in RAM................................................ Figure 18.8 Example of RAM Overlap Operation (RAM[2:0] = b'000) ................................. Figure 18.9 Program/Program-Verify Flowchart .................................................................... Figure 18.10 Erase/Erase-Verify Flowchart.............................................................................. 398 407 408 410 413 414 415 417 417 418 419 420 421 421 422 423 424 426 430 449 451 453 456 457 460 461 462 463 464 473 474 475 477 479 Rev. 4.00 Dec 05, 2005 page xxxvii of xliv Figure 18.11 Power-On/Off Timing (Boot Mode) .................................................................... 485 Figure 18.12 Power-On/Off Timing (User Program Mode)...................................................... 486 Figure 18.13 Mode Transition Timing (Example: Boot Mode User Mode User Program Mode) ........................... 487 Section 19 Mask ROM Figure 19.1 Mask ROM Block Diagram (SH7148) ................................................................ 489 Figure 19.2 Mask ROM Block Diagram (SH7048) ................................................................ 489 Section 21 Power-Down Modes Figure 21.1 Mode Transition Diagram.................................................................................... 495 Figure 21.2 NMI Timing in Software Standby Mode ............................................................. 504 Section 22 Electrical Characteristics Figure 22.1 Output Load Circuit ............................................................................................. Figure 22.2 System Clock Timing .......................................................................................... Figure 22.3 EXTAL Clock Input Timing................................................................................ Figure 22.4 Oscillation Settling Time ..................................................................................... Figure 22.5 Reset Input Timing .............................................................................................. Figure 22.6 Reset Input Timing .............................................................................................. Figure 22.7 Interrupt Signal Input Timing .............................................................................. Figure 22.8 Interrupt Signal Output Timing............................................................................ Figure 22.9 MTU Input/Output timing.................................................................................... Figure 22.10 MTU Clock Input Timing .................................................................................... Figure 22.11 I/O Port Input/Output timing ............................................................................... Figure 22.12 WDT Timing........................................................................................................ Figure 22.13 SCI Input Timing ................................................................................................. Figure 22.14 SCI Input/Output Timing ..................................................................................... Figure 22.15 MMT Input/Output Timing.................................................................................. Figure 22.16 POE Input/Output Timing.................................................................................... Figure 22.17 External Trigger Input Timing............................................................................. Figure 22.18 UBC Trigger Timing............................................................................................ 511 513 513 513 515 515 516 516 518 518 519 520 521 522 523 524 525 526 Appendix D Package Dimensions Figure D.1 PRQP0080JD-A................................................................................................... 560 Rev. 4.00 Dec 05, 2005 page xxxviii of xliv Tables Section 2 CPU Table 2.1 Initial Values of Registers ...................................................................................... 12 Table 2.2 Sign Extension of Word Data................................................................................. 14 Table 2.3 Delayed Branch Instructions .................................................................................. 15 Table 2.4 T Bit ....................................................................................................................... 15 Table 2.5 Immediate Data Accessing ..................................................................................... 16 Table 2.6 Absolute Address Accessing .................................................................................. 16 Table 2.7 Displacement Accessing......................................................................................... 17 Table 2.8 Addressing Modes and Effective Addresses .......................................................... 17 Table 2.9 Instruction Formats ................................................................................................ 21 Table 2.10 Classification of Instructions.................................................................................. 24 Section 3 MCU Operating Modes Table 3.1 Selection of Operating Modes................................................................................ 39 Table 3.2 Maximum Operating Clock Frequency for Each Clock Mode............................... 40 Table 3.3 Operating Mode Pin Configuration ........................................................................ 40 Section 4 Clock Pulse Generator Table 4.1 Damping Resistance Values ................................................................................... 48 Table 4.2 Crystal Resonator Characteristics........................................................................... 48 Section 5 Exception Processing Table 5.1 Types of Exception Processing and Priority........................................................... Table 5.2 Timing for Exception Source Detection and Start of Exception Processing .......... Table 5.3 Exception Processing Vector Table........................................................................ Table 5.4 Calculating Exception Processing Vector Table Addresses ................................... Table 5.5 Reset Status ............................................................................................................ Table 5.6 Bus Cycles and Address Errors .............................................................................. Table 5.7 Interrupt Sources .................................................................................................... Table 5.8 Interrupt Priority..................................................................................................... Table 5.9 Types of Exceptions Triggered by Instructions...................................................... Table 5.10 Generation of Exception Sources Immediately after a Delayed Branch Instruction or Interrupt-Disabled Instruction.......................................................... Table 5.11 Stack Status after Exception Processing Ends........................................................ 53 54 55 56 57 59 60 61 62 64 65 Section 6 Interrupt Controller (INTC) Table 6.1 Pin Configuration ................................................................................................... 69 Table 6.2 Interrupt Exception Processing Vectors and Priorities........................................... 80 Rev. 4.00 Dec 05, 2005 page xxxix of xliv Table 6.3 Interrupt Response Time ........................................................................................ 86 Section 8 Data Transfer Controller (DTC) Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTEs................... Table 8.2 Normal Mode Register Functions .......................................................................... Table 8.3 Repeat Mode Register Functions............................................................................ Table 8.4 Block Transfer Mode Register Functions............................................................... Table 8.5 Execution State of DTC ......................................................................................... Table 8.6 State Counts Needed for Execution State............................................................... 116 119 120 121 124 124 Section 9 Bus State Controller (BSC) Table 9.1 Address Map .......................................................................................................... 130 Table 9.2 On-chip Peripheral I/O Register Access................................................................. 132 Section 10 Table 10.1 Table 10.2 Table 10.3 Table 10.4 Table 10.5 Table 10.6 Table 10.7 Table 10.8 Table 10.9 Table 10.10 Table 10.11 Table 10.12 Table 10.13 Table 10.14 Table 10.15 Table 10.16 Table 10.17 Table 10.18 Table 10.19 Table 10.20 Table 10.21 Table 10.22 Table 10.23 Table 10.24 Table 10.25 Table 10.26 Multi-Function Timer Pulse Unit (MTU) MTU Functions ...................................................................................................... MTU Pins ............................................................................................................... CCLR0 to CCLR2 (channels 0, 3, and 4)............................................................... CCLR0 to CCLR2 (channels 1 and 2).................................................................... TPSC0 to TPSC2 (channel 0)................................................................................. TPSC0 to TPSC2 (channel 1)................................................................................. TPSC0 to TPSC2 (channel 2)................................................................................. TPSC0 to TPSC2 (channels 3 and 4) ..................................................................... MD0 to MD3.......................................................................................................... TIORH_0 (channel 0)............................................................................................. TIORH_0 (channel 0)............................................................................................. TIORL_0 (channel 0) ............................................................................................. TIORL_0 (channel 0) ............................................................................................. TIOR_1 (channel 1) ............................................................................................... TIOR_1 (channel 1) ............................................................................................... TIOR_2 (channel 2) ............................................................................................... TIOR_2 (channel 2) ............................................................................................... TIORH_3 (channel 3)............................................................................................. TIORH_3 (channel 3)............................................................................................. TIORL_3 (channel 3) ............................................................................................. TIORL_3 (channel 3) ............................................................................................. TIORH_4 (channel 4)............................................................................................. TIORH_4 (channel 4)............................................................................................. TIORL_4 (channel 4) ............................................................................................. TIORL_4 (channel 4) ............................................................................................. Output Level Select Function................................................................................. 134 137 141 141 142 142 143 143 145 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 173 Rev. 4.00 Dec 05, 2005 page xl of xliv Table 10.27 Table 10.28 Table 10.29 Table 10.30 Table 10.31 Table 10.32 Table 10.33 Table 10.34 Table 10.35 Table 10.36 Table 10.37 Table 10.38 Table 10.39 Table 10.40 Table 10.41 Table 10.42 Table 10.43 Table 10.44 Table 10.45 Output Level Select Function................................................................................. Output level Select Function .................................................................................. Register Combinations in Buffer Operation........................................................... Cascaded Combinations ......................................................................................... PWM Output Registers and Output Pins................................................................ Phase Counting Mode Clock Input Pins................................................................. Up/Down-Count Conditions in Phase Counting Mode 1 ....................................... Up/Down-Count Conditions in Phase Counting Mode 2 ....................................... Up/Down-Count Conditions in Phase Counting Mode 3 ....................................... Up/Down-Count Conditions in Phase Counting Mode 4 ....................................... Output Pins for Reset-Synchronized PWM Mode ................................................. Register Settings for Reset-Synchronized PWM Mode ......................................... Output Pins for Complementary PWM Mode........................................................ Register Settings for Complementary PWM Mode................................................ Registers and Counters Requiring Initialization..................................................... MTU Interrupts ...................................................................................................... Mode Transition Combinations.............................................................................. Pin Configuration ................................................................................................... Pin Combinations ................................................................................................... 174 176 186 189 192 196 197 198 199 200 203 203 207 208 216 234 262 295 295 Section 11 Watchdog Timer Table 11.1 Pin Configuration ................................................................................................... 304 Table 11.2 WDT Interrupt Source (in Interval Timer Mode)................................................... 313 Section 12 Serial Communication Interface (SCI) Table 12.1 Pin Configuration ................................................................................................... Table 12.2 Relationships between N Setting in BRR and Effective Bit Rate B0 ...................... Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)............................. Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2)............................. Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3)............................. Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (4)............................. Table 12.4 Maximum Bit Rate for Each Frequency when Using Baud Rate Generator (Asynchronous Mode)............................................................................................ Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode).................. Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1)................. Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2)................. Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (3)................. Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (4)................. Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)...... Table 12.8 Serial Transfer Formats (Asynchronous Mode) ..................................................... Table 12.9 SSR Status Flags and Receive Data Handling........................................................ 319 328 329 330 331 332 333 334 335 336 337 338 339 341 348 Rev. 4.00 Dec 05, 2005 page xli of xliv Table 12.10 SCI Interrupt Sources ............................................................................................. 365 Section 13 A/D Converter Table 13.1 Pin Configuration ................................................................................................... Table 13.2 Channel Select List................................................................................................. Table 13.3 A/D Conversion Time (Single Mode) .................................................................... Table 13.4 A/D Conversion Time (Scan Mode)....................................................................... Table 13.5 A/D Converter Interrupt Source ............................................................................. Table 13.6 Analog Pin Specifications ...................................................................................... 371 374 380 380 381 386 Section 15 Motor Management Timer (MMT) Table 15.1 Pin Configuration ................................................................................................... 399 Table 15.2 Initial Values of TBRU to TBRW and Initial Output............................................. 412 Table 15.3 Relationship between A/D Conversion Start Timing and Operating Mode ........... 415 Table 15.4 MMT Interrupt Sources.......................................................................................... 416 Table 15.5 Pin Configuration ................................................................................................... 427 Section 16 Pin Function Controller (PFC) Table 16.1 Multiplexed Pins (Port A) ...................................................................................... Table 16.2 Multiplexed Pins (Port B)....................................................................................... Table 16.3 Multiplexed Pins (Port E)....................................................................................... Table 16.4 Multiplexed Pins (Port F) ....................................................................................... Table 16.5 Multiplexed Pins (Port G) ...................................................................................... Table 16.6 Pin Functions in Each Mode .................................................................................. Section 17 I/O Ports Table 17.1 Port A Data Register L (PADRL) Read/Write Operations..................................... Table 17.2 Port B Data Register (PBDR) Read/Write Operations ........................................... Table 17.3 Port E Data Registers H and L (PEDRH and PEDRL) Read/Write Operations..... Table 17.4 Port F Data Register (PFDR) Read/Write Operations............................................ Table 17.5 Port G Data Register (PGDR) Read/Write Operations........................................... Section 18 Flash Memory (F-ZTAT Version) Table 18.1 Differences between Boot Mode and User Program Mode.................................... Table 18.2 Pin Configuration ................................................................................................... Table 18.3 Setting On-Board Programming Modes................................................................. Table 18.4 Boot Mode Operation............................................................................................. Table 18.5 Peripheral Clock (P) Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible....................................................................................................... 433 434 434 435 435 436 451 452 455 457 458 461 465 470 472 472 Rev. 4.00 Dec 05, 2005 page xlii of xliv Section 21 Power-Down Modes Table 21.1 Internal Operation States in Each Mode................................................................. 494 Table 21.2 Pin Configuration ................................................................................................... 496 Section 22 Table 22.1 Table 22.2 Table 22.3 Table 22.4 Table 22.5 Table 22.6 Table 22.7 Table 22.8 Table 22.9 Table 22.10 Table 22.11 Table 22.12 Table 22.13 Table 22.14 Table 22.15 Electrical Characteristics Absolute Maximum Ratings................................................................................... DC Characteristics.................................................................................................. Permitted Output Current Values ........................................................................... Clock Timing ......................................................................................................... Control Signal Timing............................................................................................ Multi-Function Timer Pulse Unit Timing .............................................................. I/O Port Timing ...................................................................................................... Watchdog Timer Timing ........................................................................................ Serial Communication Interface Timing ................................................................ Motor Management Timer Timing......................................................................... Port Output Enable (POE) Timing ......................................................................... A/D Converter Timing ........................................................................................... UBC Trigger Timing .............................................................................................. A/D Converter Characteristics ............................................................................... Flash Memory Characteristics................................................................................ 507 508 510 512 514 517 519 520 521 523 524 525 526 527 528 Appendix B Pin States Table B.1 Pin States ................................................................................................................ 557 Rev. 4.00 Dec 05, 2005 page xliii of xliv Rev. 4.00 Dec 05, 2005 page xliv of xliv Section 1 Overview Section 1 Overview The SH7046 Group single-chip RISC (Reduced Instruction Set Computer) microprocessors integrate a Renesas-original RISC CPU core with peripheral functions required for system configuration. The SH7046 Group CPU has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed. In addition, the 32-bit internal-bus architecture enhances data processing power. With this CPU, it has become possible to assemble low cost, high performance/high-functioning systems, even for applications that were previously impossible with microprocessors, such as real-time control, which demands high speeds. In addition, the SH7046 Group includes on-chip peripheral functions necessary for system configuration, such as large-capacity ROM and RAM, timers, a serial communication interface (SCI), an A/D converter, an interrupt controller (INTC), and I/O ports. There are two versions of on-chip ROM: F-ZTAT (Flexible Zero Turn Around Time) that includes flash memory, and mask ROM. The flash memory can be programmed with a programmer that supports SH7046 Group programming, and can also be programmed and erased by software. This enables LSI chip to be re-programmed at a user-site while mounted on a board. TM 1.1 Features * Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture Instruction length: 16-bit fixed length for improved code efficiency Load-store architecture (basic operations are executed between registers) Sixteen 32-bit general registers Five-stage pipeline On-chip multiplier: multiplication operations (32 bits x 32 bits 64 bits) executed in two to four cycles C language-oriented 62 basic instructions * Various peripheral functions Data transfer controller (DTC) Multifunction timer/pulse unit (MTU) Motor management timer(MMT) Compare match timer (CMT) Rev. 4.00 Dec 05, 2005 page 1 of 564 REJ09B0270-0400 Section 1 Overview Watchdog timer (WDT) Asynchronous or clocked synchronous serial communication interface(SCI) 10-bit A/D converter Clock pulse generator User break controller (UBC)* Note: * Supported only for flash memory version. * On-chip memory ROM Flash memory Version Mask ROM Version Model HD64F7046 HD6437048/ HD6437148 ROM 256 kbytes 128 kbytes/ 64 kbytes RAM 12 kbytes 4 kbytes Remarks * Maximum operating frequency and operating temperature range Maximum operating frequency (MHz) (system clock () and peripheral clock (P)) (50, 25) or (40, 40) (50, 25) or (40, 40) Model HD64F7046F50/HD6437148F50/ HD6437048F50 HD64F7046FW50/HD6437148FW50/ HD6437048FW50 Operating temperature range (C) -20 to +75 -40 to +85 * I/O ports Model HD64F7046/HD6437148/ HD6437048 No. of I/O Pins 42 No. of Input-only Pins 12 * Supports various power-down states * Compact package Model HD64F7046/HD6437148/ HD6437048 Package QFP-80 (Code) FP-80Q Body Size 14.0 Pin Pitch 0.65 mm x 14.0 mm Rev. 4.00 Dec 05, 2005 page 2 of 564 REJ09B0270-0400 Section 1 Overview 1.2 Internal Block Diagram PA9/TCLKD/IRQ3/TXD3 PA8/TCLKC/IRQ2/RXD3 PA5/IRQ1/POE6/SCK3 PA2/IRQ0/PCIO/SCK2 PA11/ADTRG/SCK3 PA6/TCLKA/RXD2 PA7/TCLKB/TXD2 PA3/POE4/RXD3 PA0/POE0/RXD2 PA4/POE5/TXD3 PA1/POE1/TXD2 PB5/IRQ3/POE3 PB4/IRQ2/POE2 PB3/IRQ1/POE1 PA12/UBCTRG PA15/POE6 PA14/POE5 PA13/POE4 RES WDTOVF MD3 MD2 MD1 MD0 NMI EXTAL XTAL PLLVcL PLLCAP PLLVss FWP * VcL VcL Vcc Vcc Vcc Vss Vss Vss Vss AVcc AVcc AVss AVss Compare match timer (x2 channels) A/D Watchdog converter timer Serial communication interface (x2 channels) Multifunction timer pulse unit Interrupt controller User break* controller Bus state controller CPU Flash ROM/mask ROM RAM PLL Data transfer controller Motor management timer (x1 channel) PG3/AN19 PG2/AN18 PG1/AN17 PG0/AN16 PF15/AN15 PF14/AN14 PF13/AN13 PF12/AN12 PF11/AN11 PF10/AN10 PF9/AN9 PF8/AN8 PA10/SCK2 PE21/PWOB PE20/PVOB PE19/PUOB PE18/PWOA PE17/PVOA PE16/PUOA/UBCTRG PE15/TIOC4D/IRQOUT PE14/TIOC4C PE13/TIOC4B/MRES PE12/TIOC4A PE11/TIOC3D PE10/TIOC3C/TXD2 PE9/TIOC3B PE8/TIOC3A/SCK2 PE7/TIOC2B/RXD2 PE6/TIOC2A/SCK3 PE5/TIOC1B/TXD3 PE4/TIOC1A/RXD3 PE3/TIOC0D PE2/TIOC0C PE1/TIOC0B PE0/TIOC0A PB2/IRQ0/POE0 : Peripheral address bus (12 bits) : Peripheral data bus (16 bits) : Internal address bus (32 bits) : Internal upper data bus (16 bits) : Internal lower data bus (16 bits) Note: * F-ZTAT version only Figure 1.1 Internal Block Diagram of SH7046 Rev. 4.00 Dec 05, 2005 page 3 of 564 REJ09B0270-0400 1.3 Section 1 Overview Pin Arrangement PA1/POE1/TXD2 VcL PA0/POE0/RXD2 Vss FWP* Vcc RES NMI MD3 MD2 MD1 MD0 EXTAL XTAL PLLVcL PLLCAP PLLVss WDTOVF PE0/TIOC0A PE1/TIOC0B 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Rev. 4.00 Dec 05, 2005 page 4 of 564 REJ09B0270-0400 QFP-80 (Top view) Note: * For the mask ROM version, connect this pin to Vcc. PE2/TIOC0C PE3/TIOC0D PE4/TIOC1A/RXD3 PE5/TIOC1B/TXD3 PE6/TIOC2A/SCK3 PE7/TIOC2B/RXD2 PE8/TIOC3A/SCK2 PE9/TIOC3B Vss PE10/TIOC3C/TXD2 Vcc PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES PE14/TIOC4C PE15/TIOC4D/IRQOUT PE16/PUOA/UBCTRG PE17/PVOA PE18/PWOA PE19/PUOB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 Figure 1.2 SH7046 Pin Arrangement 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 AVss PF8/AN8 AVcc PF9/AN9 PF10/AN10 PF11/AN11 PG0/AN16 PG1/AN17 PG2/AN18 PG3/AN19 PF12/AN12 PF13/AN13 PF14/AN14 AVcc PF15/AN15 AVss Vss PE21/PWOB VcL PE20/PVOB PA2/IRQ0/PCIO/SCK2 PA3/POE4/RXD3 PA4/POE5/TXD3 PA5/IRQ1/POE6/SCK3 PA6/TCLKA/RXD2 PA7/TCLKB/TXD2 PA8/TCLKC/IRQ2/RXD3 PA9/TCLKD/IRQ3/TXD3 PA10/SCK2 PA11/ADTRG/SCK3 PA12/UBCTRG PA13/POE4 PA14/POE5 PA15/POE6 PB2/IRQ0/POE0 PB3/IRQ1/POE1 PB4/IRQ2/POE2 Vcc PB5/IRQ3/POE3 Vss Section 1 Overview 1.4 Type Power Supply Pin Functions Symbol VCC I/O Input Name Power supply Function Power supply pins. Connect all these pins to the system power supply. The chip does not operate normally when some of these pins are open. Ground pins. Connect all these pins to the system power supply (0 V). The chip does not operate normally when some of these pins are open. External capacitance pins for internal power-down power supply. Connect this pins to VSS via a 0.47 F (-10%/+100%) capacitor (placed close to the pin). External capacitance pin for internal power-down power supply for an on-chip PLL oscillator. Connect this pin to PLLVSS via a 0.47 F (-10%/+100%) capacitor (placed close to the pin). On-chip PLL oscillator ground pin. External capacitance pin for an on-chip PLL oscillator. VSS Input Ground VCL Output Power supply for internal power-down Power supply for PLL Clock PLLVCL Output PLLVSS PLLCAP EXTAL Input Input Input Ground for PLL Capacitance for PLL External clock For connection to a crystal resonator. (An external clock can be supplied from the EXTAL pin.) For examples of crystal resonator connection and external clock input, see section 4, Clock Pulse Generator. Crystal For connection to a crystal resonator. For examples of crystal resonator connection and external clock input, see section 4, Clock Pulse Generator. XTAL Input Rev. 4.00 Dec 05, 2005 page 5 of 564 REJ09B0270-0400 Section 1 Overview Type Operating mode control Symbol MD3 MD2 MD1 MD0 FWP I/O Input Name Set the mode Function Set the operating mode. Inputs at these pins should not be changed during operation. Pin for the flash memory. This pin is only used in the flash memory version. Writing or erasing of flash memory can be protected. This pin becomes the Vcc pin for the mask ROM version. When this pin is driven low, the chip becomes to power on reset state. When this pin is driven low, the chip becomes to manual reset state. Input Protection against write operation into Flash memory Power on reset Manual reset System control RES MRES WDTOVF Input Input Output Watchdog Output signal for the watchdog timer timer overflow overflow. If this pin need to be pulleddown, use the resistor larger than 1 M to pull the pin down. Nonmaskable interrupt Interrupt request 3 to 0 Non-maskable interrupt pin. If this pin is not used, it should be fixed high. These pins request a maskable interrupt. One of the level input or edge input can be selected. In case of the edge input, one of the rising edge, falling edge, or both can be selected. Interrupts NMI Input IRQ3 IRQ2 IRQ1 IRQ0 IRQOUT Multi function timer-pulse unit (MTU) TCLKA TCLKB TCLKC TCLKD TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B Input Output Input Interrupt Shows that an interrupt cause has request output occurred. External clock These pins input an external clock. input for MTU timer MTU input The TGRA_0 to TGRD_0 input capture capture/output input/output compare output/PWM output compare pins. (channel 0) MTU input The TGRA_1 to TGRB_1 input capture capture/output input/output compare output/PWM output compare pins. (channel 1) Input/ Output Input/ Output Rev. 4.00 Dec 05, 2005 page 6 of 564 REJ09B0270-0400 Section 1 Overview Type Multi function timer-pulse unit (MTU) Symbol TIOC2A TIOC2B I/O Input/ Output Name Function MTU input The TGRA_2 to TGRB_2 input capture capture/output input/output compare output/PWM output compare pins. (channel 2) MTU input The TGRA_3 to TGRD_3 input capture capture/output input/output compare output/PWM output compare pins. (channel 3) MTU input The TGRA_4 to TGRD_4 input capture capture/output input/output compare output/PWM output compare pins. (channel 4) Transmitted data Data output pins. TIOC3A TIOC3B TIOC3C TIOC3D TIOC4A TIOC4B TIOC4C TIOC4D Serial communication Interface (SCI) TxD2 TxD3 RxD2 RxD3 SCK2 SCK3 Motor PUOA managemen t timer PUOB (MMT) PVOA PVOB PWOA PWOB PCIO Input/ Output Input/ Output Output Input Input/ Output Output Output Output Output Output Output Input/ Output Input Received data Data input pins. Serial clock U-phase of PWM U-phase of PWM V-phase of PWM V-phase of PWM W-phase of PWM W-phase of PWM PWM control Clock input/output pins. U-phase output pin for 6-phase nonoverlap PWM waveforms. U-phase output pin for 6-phase nonoverlap PWM waveforms. V-phase output pin for 6-phase nonoverlap PWM waveforms. V-phase output pin for 6-phase nonoverlap PWM waveforms. W-phase output pin for 6-phase nonoverlap PWM waveforms. W-phase output pin for 6-phase nonoverlap PWM waveforms. Counter clear input pin by external input or output pin for toggle synchronized with PWM period. Input pins for the signal to request the output pins of MTU or MMT to become high impedance state. Output control for MTU and MMT POE6 to POE0 Port output control Rev. 4.00 Dec 05, 2005 page 7 of 564 REJ09B0270-0400 Section 1 Overview Type A/D converter Symbol I/O Name Analog input pins Function Analog input pins. AN19 to AN8 Input ADTRG Input Input of Pin for input of an external trigger to start trigger for A/D A/D conversion conversion Analog power supply Power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply (+5 V). Connect all AVCC pins to the power supply. The chip does not operate normally when some of these pins are open. The ground pin for the A/D converter. Connect this pin to the system power supply (0 V). Connect all AVSS pins to the system power supply The chip does not operate normally when some of these pins are open. 16-bits general purpose input/output pins 4-bits general purpose input/output pins. 22-bits general purpose input/output pins. 8-bits general purpose input pins. 4-bits general purpose input pins. UBC condition match trigger output pin. AVCC Input AVSS Input Analog ground I/O ports PA15 to PA0 Input/ Output PB5 to PB2 Input/ Output General purpose port General purpose port General purpose port General purpose port General purpose port User break trigger output PE21 to PE0 Input/ Output PF15 to PF8 PG3 to PG0 User break UBCTRG controller (UBC) (flash version only) Input Input Output Rev. 4.00 Dec 05, 2005 page 8 of 564 REJ09B0270-0400 Section 2 CPU Section 2 CPU 2.1 Features * General-register architecture Sixteen 32-bit general registers * Sixty-two basic instructions * Eleven addressing modes Register direct [Rn] Register indirect [@Rn] Register indirect with post-increment [@Rn+] Register indirect with pre-decrement [@-Rn] Register indirect with displacement [@disp:4,Rn] Register indirect with index [@R0, Rn] GBR indirect with displacement [@disp:8,GBR] GBR indirect with index [@R0,GBR] Program-counter relative with displacement [@disp:8,PC] Program-counter relative [disp:8/disp:12/Rn] Immediate [#imm:8] 2.2 Register Configuration The register set consists of sixteen 32-bit general registers, three 32-bit control registers, and four 32-bit system registers. 2.2.1 General Registers (Rn) The sixteen 32-bit general registers (Rn) are numbered R0-R15. General registers are used for data processing and address calculation. R0 is also used as an index register. Several instructions have R0 fixed as their only usable register. R15 is used as the hardware stack pointer (SP). Saving and recovering the status register (SR) and program counter (PC) in exception processing is accomplished by referencing the stack using R15. CPUS200B-000020020700 Rev. 4.00 Dec 05, 2005 page 9 of 564 REJ09B0270-0400 Section 2 CPU General registers (Rn) 31 R0*1 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15, SP (hardware stack pointer)*2 0 Status register (SR) 31 9 8765 43 210 M Q I3 I2 I1 I0 ST Global base register (GBR) 31 GBR 0 Vector base register (VBR) 31 VBR 0 Multiply-accumulate register (MAC) 31 MACH MACL 0 Procedure register (PR) 31 PR 0 Program counter (PC) 31 PC 0 Notes: 1. R0 functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR addressing mode. In some instructions, R0 functions as a fixed source register or destination register. 2. R15 functions as a hardware stack pointer (SP) during exception processing. Figure 2.1 CPU Internal Registers Rev. 4.00 Dec 05, 2005 page 10 of 564 REJ09B0270-0400 Section 2 CPU 2.2.2 Control Registers The control registers consist of three 32-bit registers: status register (SR), global base register (GBR), and vector base register (VBR). The status register indicates processing states. The global base register functions as a base address for the indirect GBR addressing mode to transfer data to the registers of on-chip peripheral modules. The vector base register functions as the base address of the exception processing vector area (including interrupts). Status Register (SR): Bit 31 to 10 9 8 7 to 4 3, 2 Bit Name Initial Value All 0 R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. M Q I3 to I0 Undefined Undefined All 1 All 0 R/W R/W R/W R/W Used by the DIV0U, DIV0S, and DIV1 instructions. Used by the DIV0U, DIV0S, and DIV1 instructions. Interrupt mask bits. Reserved These bits are always read as 0. The write value should always be 0. 1 0 S T Undefined Undefined R/W R/W S bit Used by the MAC instruction. T bit The MOVT, CMP/cond, TAS, TST, BT (BT/S), BF (BF/S), SETT, and CLRT instructions use the T bit to indicate true (1) or false (0). The ADDV, ADDC, SUBV, SUBC, DIV0U, DIV0S, DIV1, NEGC, SHAR, SHAL, SHLR, SHLL, ROTR, ROTL, ROTCR, and ROTCL instructions also use the T bit to indicate carry/borrow or overflow/underflow. Global Base Register (GBR): Indicates the base address of the indirect GBR addressing mode. The indirect GBR addressing mode is used in data transfer for on-chip peripheral modules register areas and in logic operations. Vector Base Register (VBR): Indicates the base address of the exception processing vector area. Rev. 4.00 Dec 05, 2005 page 11 of 564 REJ09B0270-0400 Section 2 CPU 2.2.3 System Registers System registers consist of four 32-bit registers: high and low multiply and accumulate registers (MACH and MACL), the procedure register (PR), and the program counter (PC). Multiply-and-Accumulate Registers (MAC): Registers to store the results of multiply-andaccumulate operations. Procedure Register (PR): Registers to store the return address from a subroutine procedure. Program Counter (PC): Registers to indicate the sum of current instruction addresses and four, that is, the address of the second instruction after the current instruction. 2.2.4 Initial Values of Registers Table 2.1 lists the values of the registers after reset. Table 2.1 Initial Values of Registers Register R0-R14 R15 (SP) Control registers SR GBR VBR System registers MACH, MACL, PR PC Initial Value Undefined Value of the stack pointer in the vector address table Bits I3-I0 are 1111 (H'F), reserved bits are 0, and other bits are undefined Undefined H'00000000 Undefined Value of the program counter in the vector address table Classification General registers Rev. 4.00 Dec 05, 2005 page 12 of 564 REJ09B0270-0400 Section 2 CPU 2.3 2.3.1 Data Formats Data Format in Registers Register operands are always longwords (32 bits). If the size of memory operand is a byte (8 bits) or a word (16 bits), it is changed into a longword by expanding the sign-part when loaded into a register. 31 Longword 0 Figure 2.2 Data Format in Registers 2.3.2 Data Formats in Memory Memory data formats are classified into bytes, words, and longwords. Byte data can be accessed from any address. Locate, however, word data at an address 2n, longword data at 4n. Otherwise, an address error will occur if an attempt is made to access word data starting from an address other than 2n or longword data starting from an address other than 4n. In such cases, the data accessed cannot be guaranteed. The hardware stack area, pointed by the hardware stack pointer (SP, R15), uses only longword data starting from address 4n because this area holds the program counter and status register. Address m + 1 Address m 31 Byte Address 2n Address 4n Word Longword 23 Byte Address m + 3 Address m + 2 15 Byte Word 7 Byte 0 Figure 2.3 Data Formats in Memory Rev. 4.00 Dec 05, 2005 page 13 of 564 REJ09B0270-0400 Section 2 CPU 2.3.3 Immediate Data Format Byte (8 bit) immediate data resides in an instruction code. Immediate data accessed by the MOV, ADD, and CMP/EQ instructions is sign-extended and handled in registers as longword data. Immediate data accessed by the TST, AND, OR, and XOR instructions is zero-extended and handled as longword data. Consequently, AND instructions with immediate data always clear the upper 24 bits of the destination register. Word or longword immediate data is not located in the instruction code, but instead is stored in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement. 2.4 2.4.1 Instruction Features RISC-Type Instruction Set All instructions are RISC type. This section details their functions. 16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency. One Instruction per State: The microprocessor can execute basic instructions in one state using the pipeline system. One state is 25 ns at 40 MHz. Data Length: Longword is the standard data length for all operations. Memory can be accessed in bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and handled as longword data. Immediate data is sign-extended for arithmetic operations or zeroextended for logic operations. It also is handled as longword data. Table 2.2 Sign Extension of Word Data Description Example of Conventional CPU #H'1234,R0 CPU of This LSI MOV.W ADD @(disp,PC),R1 R1,R0 ......... .DATA.W H'1234 Data is sign-extended to 32 ADD.W bits, and R1 becomes H'00001234. It is next operated upon by an ADD instruction. Note: @(disp, PC) accesses the immediate data. Rev. 4.00 Dec 05, 2005 page 14 of 564 REJ09B0270-0400 Section 2 CPU Load-Store Architecture: Basic operations are executed between registers. For operations that involve memory access, data is loaded to the registers and executed (load-store architecture). Instructions such as AND that manipulate bits, however, are executed directly in memory. Delayed Branch Instructions: Unconditional branch instructions are delayed branch instructions. With a delayed branch instruction, the branch is taken after execution of the instruction following the delayed branch instruction. This reduces the disturbance of the pipeline control in case of branch instructions. There are two types of conditional branch instructions: delayed branch instructions and ordinary branch instructions. Table 2.3 Delayed Branch Instructions Description Executes the ADD before branching to TRGET. Example of Conventional CPU ADD.W BRA R1,R0 TRGET CPU of This LSI BRA ADD TRGET R1,R0 Multiply/Multiply-and-Accumulate Operations: 16-bit x 16-bit 32-bit multiply operations are executed in one to two states. 16-bit x 16-bit + 64-bit 64-bit multiply-and-accumulate operations are executed in two to three states. 32-bit x 32-bit 64-bit multiply and 32-bit x 32-bit + 64-bit 64-bit multiply-and-accumulate operations are executed in two to four states. T Bit: The T bit in the status register changes according to the result of the comparison. Whether a conditional branch is taken or not taken depends upon the T bit condition (true/false). The number of instructions that change the T bit is kept to a minimum to improve the processing speed. Table 2.4 T Bit Description T bit is set when R0 R1. The program branches to TRGET0 when R0 R1 and to TRGET1 when R0 < R1. T bit is not changed by ADD. T bit is set when R0 = 0. The program branches if R0 = 0. Example of Conventional CPU CMP.W BGE BLT SUB.W BEQ R1,R0 TRGET0 TRGET1 #1,R0 TRGET CPU of This LSI CMP/GE BT BF ADD CMP/EQ BT R1,R0 TRGET0 TRGET1 #-1,R0 #0,R0 TRGET Rev. 4.00 Dec 05, 2005 page 15 of 564 REJ09B0270-0400 Section 2 CPU Immediate Data: Byte (8-bit) immediate data is located in an instruction code. Word or longword immediate data is not located in instruction codes but in a memory table. An immediate data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode with displacement. Table 2.5 Immediate Data Accessing CPU of This LSI MOV MOV.W #H'12,R0 @(disp,PC),R0 ................. .DATA.W 32-bit immediate MOV.L H'1234 @(disp,PC),R0 ................. .DATA.L H'12345678 Note: @(disp, PC) accesses the immediate data. MOV.L #H'12345678,R0 Example of Conventional CPU MOV.B MOV.W #H'12,R0 #H'1234,R0 Classification 8-bit immediate 16-bit immediate Absolute Address: When data is accessed by absolute address, the value in the absolute address is placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in the indirect register addressing mode. Table 2.6 Absolute Address Accessing CPU of This LSI MOV.L MOV.B @(disp,PC),R1 @R1,R0 .................. .DATA.L H'12345678 Note: @(disp,PC) accesses the immediate data. Example of Conventional CPU MOV.B @H'12345678,R0 Classification Absolute address Rev. 4.00 Dec 05, 2005 page 16 of 564 REJ09B0270-0400 Section 2 CPU 16-Bit/32-Bit Displacement: When data is accessed by 16-bit or 32-bit displacement, the displacement value is placed in the memory table in advance. That value is transferred to the register by loading the immediate data during the execution of the instruction, and the data is accessed in the indirect indexed register addressing mode. Table 2.7 Displacement Accessing CPU of This LSI MOV.W MOV.W @(disp,PC),R0 @(R0,R1),R2 .................. .DATA.W H'1234 Note: @(disp,PC) accesses the immediate data. Example of Conventional CPU MOV.W @(H'1234,R1),R2 Classification 16-bit displacement 2.4.2 Addressing Modes Table 2.8 describes addressing modes and effective address calculation. Table 2.8 Addressing Mode Direct register addressing Addressing Modes and Effective Addresses Instruction Format Effective Address Calculation Rn The effective address is register Rn. (The operand is the contents of register Rn.) Equation Indirect register @Rn addressing Post-increment @Rn+ indirect register addressing The effective address is the contents of register Rn. Rn Rn Rn The effective address is the contents of register Rn. A constant is added to the content of Rn after the instruction is executed. 1 is added for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn + 1/2/4 1/2/4 + Rn Rn (After the instruction executes) Byte: Rn + 1 Rn Word: Rn + 2 Rn Longword: Rn + 4 Rn Rev. 4.00 Dec 05, 2005 page 17 of 564 REJ09B0270-0400 Section 2 CPU Addressing Mode Instruction Format Effective Address Calculation The effective address is the value obtained by subtracting a constant from Rn. 1 is subtracted for a byte operation, 2 for a word operation, and 4 for a longword operation. Rn Rn - 1/2/4 1/2/4 - Rn - 1/2/4 Equation Byte: Rn - 1 Rn Word: Rn - 2 Rn Longword: Rn - 4 Rn (Instruction is executed with Rn after this calculation) Byte: Rn + disp Word: Rn + disp x 2 Longword: Rn + disp x 4 Pre-decrement @-Rn indirect register addressing Indirect register @(disp:4, The effective address is the sum of Rn and a 4-bit addressing with Rn) displacement (disp). The value of disp is zerodisplacement extended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. Rn disp (zero-extended) x 1/2/4 + Rn + disp x 1/2/4 Indirect indexed register addressing @(R0, Rn) The effective address is the sum of Rn and R0. Rn + R0 Rn + R0 Rn + R0 Rev. 4.00 Dec 05, 2005 page 18 of 564 REJ09B0270-0400 Section 2 CPU Addressing Mode Instruction Format Effective Address Calculation Equation Byte: GBR + disp Word: GBR + disp x 2 Longword: GBR + disp x 4 Indirect GBR @(disp:8, The effective address is the sum of GBR value and addressing with GBR) an 8-bit displacement (disp). The value of disp is displacement zero-extended, and remains unchanged for a byte operation, is doubled for a word operation, and is quadrupled for a longword operation. GBR disp (zero-extended) x 1/2/4 + GBR + disp x 1/2/4 Indirect indexed GBR addressing @(R0, GBR) The effective address is the sum of GBR value and R0. GBR + R0 GBR + R0 GBR + R0 Indirect PC @(disp:8, The effective address is the sum of PC value and addressing with PC) an 8-bit displacement (disp). The value of disp is displacement zero-extended, and is doubled for a word operation, and quadrupled for a longword operation. For a longword operation, the lowest two bits of the PC value are masked. PC & H'FFFFFFFC disp (zero-extended) x 2/4 (for longword) PC + disp x 2 or PC & H'FFFFFFFC + disp x 4 Word: PC + disp x 2 Longword: PC & H'FFFFFFFC + disp x 4 + Rev. 4.00 Dec 05, 2005 page 19 of 564 REJ09B0270-0400 Section 2 CPU Addressing Mode PC relative addressing Instruction Format Effective Address Calculation disp:8 The effective address is the sum of PC value and the value that is obtained by doubling the signextended 8-bit displacement (disp). PC disp (sign-extended) x 2 + PC + disp x 2 Equation PC + disp x 2 disp:12 The effective address is the sum of PC value and the value that is obtained by doubling the signextended 12-bit displacement (disp). PC disp (sign-extended) x 2 + PC + disp x 2 PC + disp x 2 Rn The effective address is the sum of the register PC and Rn. PC + Rn PC + Rn PC + Rn Immediate addressing #imm:8 #imm:8 #imm:8 The 8-bit immediate data (imm) for the TST, AND, OR, and XOR instructions is zero-extended. The 8-bit immediate data (imm) for the MOV, ADD, and CMP/EQ instructions is sign-extended. The 8-bit immediate data (imm) for the TRAPA instruction is zero-extended and then quadrupled. Rev. 4.00 Dec 05, 2005 page 20 of 564 REJ09B0270-0400 Section 2 CPU 2.4.3 Instruction Format The instruction formats and the meaning of source and destination operand are described below. The meaning of the operand depends on the instruction code. The symbols used are as follows: * xxxx: Instruction code * mmmm: Source register * nnnn: Destination register * iiii: Immediate data * dddd: Displacement Table 2.9 Instruction Formats Source Operand 0 xxxx xxxx xxxx xxxx Instruction Formats 0 format 15 Destination Operand Example NOP n format 15 xxxx nnnn xxxx xxxx 0 Control register or system register Control register or system register nnnn: Direct register nnnn: Direct register nnnn: Indirect predecrement register Control register or system register Control register or system register MOVT STS Rn MACH,Rn STC.L SR,@-Rn LDC Rm,SR m format 15 xxxx mmmm xxxx xxxx 0 mmmm: Direct register mmmm: Indirect post-increment register mmmm: Indirect register mmmm: PC relative using Rm LDC.L @Rm+,SR JMP BRAF @Rm Rm Rev. 4.00 Dec 05, 2005 page 21 of 564 REJ09B0270-0400 Section 2 CPU Source Operand 0 xxxx nnnn mmmm xxxx Instruction Formats nm format 15 Destination Operand nnnn: Direct register nnnn: Indirect register MACH, MACL Example ADD Rm,Rn mmmm: Direct register mmmm: Direct register mmmm: Indirect post-increment register (multiplyand-accumulate) nnnn*: Indirect post-increment register (multiplyand-accumulate) mmmm: Indirect post-increment register mmmm: Direct register mmmm: Direct register MOV.L Rm,@Rn MAC.W @Rm+,@Rn+ nnnn: Direct register nnnn: Indirect predecrement register nnnn: Indirect indexed register R0 (Direct register) MOV.L @Rm+,Rn MOV.L Rm,@-Rn MOV.L Rm,@(R0,Rn) MOV.B @(disp,Rn),R0 md format 15 xxxx xxxx mmmm dddd 0 mmmmdddd: Indirect register with displacement nd4 format 15 xxxx xxxx nnnn dddd 0 R0 (Direct register) nnnndddd: Indirect register with displacement mmmm: Direct register mmmmdddd: Indirect register with displacement nnnndddd: Indirect register with displacement nnnn: Direct register MOV.B R0,@(disp,Rn) nmd format 15 xxxx nnnn mmmm dddd 0 MOV.L Rm,@(disp,Rn) MOV.L @(disp,Rm),Rn Rev. 4.00 Dec 05, 2005 page 22 of 564 REJ09B0270-0400 Section 2 CPU Source Operand 0 xxxx xxxx dddd dddd Instruction Formats d format 15 Destination Operand Example dddddddd: Indirect GBR with displacement R0 (Direct register) MOV.L @(disp,GBR),R0 MOV.L R0,@(disp,GBR) R0 (Direct register) dddddddd: Indirect GBR with displacement dddddddd: PC relative with displacement d12 format 15 xxxx dddd dddd dddd 0 R0 (Direct register) MOVA @(disp,PC),R0 dddddddd: PC relative dddddddddddd: PC relative BF BRA label label (label = disp + PC) MOV.L @(disp,PC),Rn nd8 format 15 xxxx nnnn dddd dddd 0 dddddddd: PC relative with displacement iiiiiiii: Immediate nnnn: Direct register i format 15 xxxx xxxx iiii iiii 0 Indirect indexed GBR nnnn: Direct register AND.B #imm,@(R0,GBR) #imm,R0 #imm #imm,Rn iiiiiiii: Immediate iiiiiiii: Immediate iiiiiiii: Immediate 0 R0 (Direct register) AND TRAPA ADD ni format 15 xxxx nnnn iiii iiii Note: * In multiply-and-accumulate instructions, nnnn is the source register. Rev. 4.00 Dec 05, 2005 page 23 of 564 REJ09B0270-0400 Section 2 CPU 2.5 2.5.1 Instruction Set Instruction Set by Classification Table 2.10 lists the instructions according to their classification. Table 2.10 Classification of Instructions Classification Types Data transfer 5 Operation Code MOV Function Data transfer, immediate data transfer, peripheral module data transfer, structure data transfer Effective address transfer T bit transfer Swap of upper and lower bytes Extraction of the middle of registers connected Binary addition Binary addition with carry Binary addition with overflow check Comparison Division Initialization of signed division Initialization of unsigned division Signed double-length multiplication Unsigned double-length multiplication Decrement and test Sign extension Zero extension Multiply-and-accumulate, double-length multiply-and-accumulate operation Double-length multiply operation Signed multiplication Unsigned multiplication Negation 33 No. of Instructions 39 MOVA MOVT SWAP XTRCT Arithmetic operations 21 ADD ADDC ADDV CMP/cond DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC MUL MULS MULU NEG Rev. 4.00 Dec 05, 2005 page 24 of 564 REJ09B0270-0400 Section 2 CPU Operation Code NEGC SUB SUBC SUBV Logic operations 6 AND NOT OR TAS TST XOR Shift 10 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn Branch 9 BF BT BRA BRAF BSR BSRF JMP JSR RTS No. of Instructions 33 Classification Types Arithmetic operations 21 Function Negation with borrow Binary subtraction Binary subtraction with borrow Binary subtraction with underflow Logical AND Bit inversion Logical OR Memory test and bit set Logical AND and T bit set Exclusive OR One-bit left rotation One-bit right rotation One-bit left rotation with T bit One-bit right rotation with T bit One-bit arithmetic left shift One-bit arithmetic right shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift Conditional branch, conditional branch with delay (Branch when T = 0) Conditional branch, conditional branch with delay (Branch when T = 1) Unconditional branch Unconditional branch Branch to subroutine procedure Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure 14 14 11 Rev. 4.00 Dec 05, 2005 page 25 of 564 REJ09B0270-0400 Section 2 CPU Operation Code CLRT CLRMAC LDC LDS NOP RTE SETT SLEEP STC STS TRAPA Total: 62 No. of Instructions 31 Classification Types System control 11 Function T bit clear MAC register clear Load to control register Load to system register No operation Return from exception processing T bit set Transition to power-down mode Store control register data Store system register data Trap exception handling 142 The table below shows the format of instruction codes, operation, and execution states. They are described by using this format according to their classification. Rev. 4.00 Dec 05, 2005 page 26 of 564 REJ09B0270-0400 Section 2 CPU Instruction Code Format Item Instruction Format Described in mnemonic. OP.Sz SRC,DEST Explanation OP: Operation code Sz: Size SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data 2 disp: Displacement* mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 1111: R15 iiii: Immediate data dddd: Displacement Direction of transfer Memory operand Flag bits in the SR Logical AND of each bit Logical OR of each bit Exclusive OR of each bit Logical NOT of each bit n-bit left shift n-bit right shift Value when no wait states are inserted* 1 Instruction code Described in MSB LSB order Outline of the Operation , (xx) M/Q/T & | ^ ~ < Execution states T bit Value of T bit after instruction is executed. An em-dash () in the column means no change. Notes: 1. Instruction execution states: The execution states shown in the table are minimums. The actual number of states may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory register) equals to the register used by the next instruction. 2. Depending on the operand size, displacement is scaled by x1, x2, or x4. For details, refer the SH-1/SH-2/SH-DSP Programming Manual. Rev. 4.00 Dec 05, 2005 page 27 of 564 REJ09B0270-0400 Section 2 CPU Data Transfer Instructions Instruction MOV MOV.W MOV.L MOV MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W #imm,Rn @(disp,PC),Rn @(disp,PC),Rn Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn @Rm,Rn @Rm,Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn @Rm+,Rn @Rm+,Rn @Rm+,Rn R0,@(disp,Rn) R0,@(disp,Rn) Rm,@(disp,Rn) @(disp,Rm),R0 @(disp,Rm),R0 @(disp,Rm),Rn Rm,@(R0,Rn) Rm,@(R0,Rn) Instruction Code Operation Execution States T Bit 1110nnnniiiiiiii #imm Sign extension 1 Rn 1001nnnndddddddd (disp x 2 + PC) Sign extension Rn 1101nnnndddddddd (disp x 4 + PC) Rn 0110nnnnmmmm0011 Rm Rn 0010nnnnmmmm0000 Rm (Rn) 0010nnnnmmmm0001 Rm (Rn) 0010nnnnmmmm0010 Rm (Rn) 1 1 1 1 1 1 0110nnnnmmmm0000 (Rm) Sign extension 1 Rn 0110nnnnmmmm0001 (Rm) Sign extension 1 Rn 0110nnnnmmmm0010 (Rm) Rn 0010nnnnmmmm0100 Rn-1 Rn, Rm (Rn) 0010nnnnmmmm0101 Rn-2 Rn, Rm (Rn) 0010nnnnmmmm0110 Rn-4 Rn, Rm (Rn) 1 1 1 1 0110nnnnmmmm0100 (Rm) Sign extension 1 Rn,Rm + 1 Rm 0110nnnnmmmm0101 (Rm) Sign extension 1 Rn,Rm + 2 Rm 0110nnnnmmmm0110 (Rm) Rn,Rm + 4 Rm 1 10000000nnnndddd R0 (disp + Rn) 10000001nnnndddd R0 (disp x 2 + Rn) 0001nnnnmmmmdddd Rm (disp x 4 + Rn) 10000100mmmmdddd (disp + Rm) Sign extension R0 10000101mmmmdddd (disp x 2 + Rm) Sign extension R0 0101nnnnmmmmdddd (disp x 4 + Rm) Rn 0000nnnnmmmm0100 Rm (R0 + Rn) 0000nnnnmmmm0101 Rm (R0 + Rn) 1 1 1 1 1 1 1 1 Rev. 4.00 Dec 05, 2005 page 28 of 564 REJ09B0270-0400 Section 2 CPU Execution States T Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Instruction MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W MOV.L MOVA MOVT Rm,@(R0,Rn) @(R0,Rm),Rn @(R0,Rm),Rn @(R0,Rm),Rn Instruction Code Operation 0000nnnnmmmm0110 Rm (R0 + Rn) 0000nnnnmmmm1100 (R0 + Rm) Sign extension Rn 0000nnnnmmmm1101 (R0 + Rm) Sign extension Rn 0000nnnnmmmm1110 (R0 + Rm) Rn R0,@(disp,GBR) 11000000dddddddd R0 (disp + GBR) R0,@(disp,GBR) 11000001dddddddd R0 (disp x 2 + GBR) R0,@(disp,GBR) 11000010dddddddd R0 (disp x 4 + GBR) @(disp,GBR),R0 11000100dddddddd (disp + GBR) Sign extension R0 @(disp,GBR),R0 11000101dddddddd (disp x 2 + GBR) Sign extension R0 @(disp,GBR),R0 11000110dddddddd (disp x 4 + GBR) R0 @(disp,PC),R0 Rn 11000111dddddddd disp x 4 + PC R0 0000nnnn00101001 T Rn 0110nnnnmmmm1000 Rm Swap bottom two bytes Rn 0110nnnnmmmm1001 Rm Swap two consecutive words Rn 0010nnnnmmmm1101 Rm: Middle 32 bits of Rn Rn SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn Rev. 4.00 Dec 05, 2005 page 29 of 564 REJ09B0270-0400 Section 2 CPU Arithmetic Operation Instructions Instruction ADD ADD ADDC ADDV CMP/EQ CMP/EQ CMP/HS CMP/GE CMP/HI CMP/GT CMP/PL CMP/PZ Rm,Rn #imm,Rn Rm,Rn Rm,Rn #imm,R0 Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rn Rn Instruction Code Operation Execution States T Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result 0 0011nnnnmmmm1100 Rn + Rm Rn 0111nnnniiiiiiii Rn + imm Rn 0011nnnnmmmm1110 Rn + Rm + T Rn, Carry T 0011nnnnmmmm1111 Rn + Rm Rn, Overflow T 10001000iiiiiiii If R0 = imm, 1 T 0011nnnnmmmm0000 If Rn = Rm, 1 T 0011nnnnmmmm0010 If Rn Rm with unsigned data, 1 T 0011nnnnmmmm0011 If Rn Rm with signed data, 1 T 0011nnnnmmmm0110 If Rn > Rm with unsigned data, 1 T 0011nnnnmmmm0111 If Rn > Rm with signed data, 1 T 0100nnnn00010101 If Rn > 0, 1 T 0100nnnn00010001 If Rn 0, 1 T 0010nnnnmmmm1100 If Rn and Rm have an equivalent byte, 1T 0011nnnnmmmm0100 Single-step division (Rn / Rm) 0010nnnnmmmm0111 MSB of Rn Q, MSB of Rm M, M ^ Q T 0000000000011001 0 M/Q/T 0011nnnnmmmm1101 Signed operation of Rn x Rm MACH, MACL 32 x 32 64 bits CMP/STR Rm,Rn DIV1 DIV0S DIV0U Rm,Rn Rm,Rn 1 1 1 2 to 4* DMULS.L Rm,Rn DMULU.L Rm,Rn 0011nnnnmmmm0101 Unsigned operation of 2 to 4* Rn x Rm MACH, MACL 32 x 32 64 bits Rev. 4.00 Dec 05, 2005 page 30 of 564 REJ09B0270-0400 Section 2 CPU Execution States T Bit 1 Comparison result Instruction DT Rn Instruction Code Operation 0100nnnn00010000 Rn - 1 Rn, when Rn is 0, 1 T. When Rn is nonzero, 0 T 0110nnnnmmmm1110 Byte in Rm is signextended Rn 0110nnnnmmmm1111 Word in Rm is signextended Rn 0110nnnnmmmm1100 Byte in Rm is zeroextended Rn 0110nnnnmmmm1101 Word in Rm is zeroextended Rn EXTS.B EXTS.W EXTU.B EXTU.W MAC.L Rm,Rn Rm,Rn Rm,Rn Rm,Rn 1 1 1 1 @Rm+,@Rn+ 0000nnnnmmmm1111 Signed operation of (Rn) x (Rm) + MAC MAC 32 x 32 + 64 64 bits @Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of (Rn) x (Rm) + MAC MAC 16 x 16 + 64 64 bits Rm,Rn Rm,Rn 0000nnnnmmmm0111 Rn x Rm MACL, 32 x 32 32 bits 0010nnnnmmmm1111 Signed operation of Rn x Rm MACL 16 x 16 32 bits 0010nnnnmmmm1110 Unsigned operation of Rn x Rm MACL 16 x 16 32 bits 0110nnnnmmmm1011 0 - Rm Rn 0110nnnnmmmm1010 0 - Rm - T Rn, Borrow T 0011nnnnmmmm1000 Rn - Rm Rn 0011nnnnmmmm1010 Rn - Rm - T Rn, Borrow T 0011nnnnmmmm1011 Rn - Rm Rn, Underflow T 3/(2 to 4)* MAC.W 3/(2)* MUL.L MULS.W 2 to 4* 1 to 3* MULU.W Rm,Rn 1 to 3* NEG NEGC SUB SUBC SUBV Note: * Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn 1 1 1 1 1 Borrow Borrow Overflow The normal number of execution states is shown. (The number in parentheses is the number of states when there is contention with the preceding or following instructions.) Rev. 4.00 Dec 05, 2005 page 31 of 564 REJ09B0270-0400 Section 2 CPU Logic Operation Instructions Instruction AND AND AND.B NOT OR OR OR.B TAS.B TST TST TST.B XOR XOR XOR.B Rm,Rn #imm,R0 Instruction Code Operation Execution States T Bit 1 1 3 1 1 1 3 4 1 1 3 1 1 3 Test result Test result Test result Test result 0010nnnnmmmm1001 Rn & Rm Rn 11001001iiiiiiii R0 & imm R0 #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR) & imm (R0 + GBR) Rm,Rn Rm,Rn #imm,R0 0110nnnnmmmm0111 ~Rm Rn 0010nnnnmmmm1011 Rn | Rm Rn 11001011iiiiiiii R0 | imm R0 #imm,@(R0,GBR) 11001111iiiiiiii (R0 + GBR) | imm (R0 + GBR) @Rn Rm,Rn #imm,R0 0100nnnn00011011 If (Rn) is 0, 1 T; 1 MSB of (Rn) 0010nnnnmmmm1000 Rn & Rm; if the result is 0, 1 T 11001000iiiiiiii R0 & imm; if the result is 0, 1 T #imm,@(R0,GBR) 11001100iiiiiiii (R0 + GBR) & imm; if the result is 0, 1 T Rm,Rn #imm,R0 0010nnnnmmmm1010 Rn ^ Rm Rn 11001010iiiiiiii R0 ^ imm R0 #imm,@(R0,GBR) 11001110iiiiiiii (R0 + GBR) ^ imm (R0 + GBR) Rev. 4.00 Dec 05, 2005 page 32 of 564 REJ09B0270-0400 Section 2 CPU Shift Instructions Instruction ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Instruction Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnn00100000 0100nnnn00100001 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 Operation T Rn MSB LSB Rn T T Rn T T Rn T T Rn 0 MSB Rn T T Rn 0 0 Rn T Rn<<2 Rn Rn>>2 Rn Rn<<8 Rn Rn>>8 Rn Rn<<16 Rn Rn>>16 Rn Execution States 1 1 1 1 1 1 1 1 1 1 1 1 1 1 T Bit MSB LSB MSB LSB MSB LSB MSB LSB SHLL16 Rn SHLR16 Rn Rev. 4.00 Dec 05, 2005 page 33 of 564 REJ09B0270-0400 Section 2 CPU Branch Instructions Instruction BF label Instruction Code 10001011dddddddd 10001111dddddddd 10001001dddddddd 10001101dddddddd 1010dddddddddddd 0000mmmm00100011 1011dddddddddddd 0000mmmm00000011 0100mmmm00101011 0100mmmm00001011 0000000000001011 * Operation If T = 0, disp x 2 + PC PC; if T = 1, nop Delayed branch, if T = 0, disp x 2 + PC PC; if T = 1, nop If T = 1, disp x 2 + PC PC; if T = 0, nop Delayed branch, if T = 1, disp x 2 + PC PC; if T = 0, nop Delayed branch, disp x 2 + PC PC Delayed branch, Rm + PC PC Delayed branch, PC PR, disp x 2 + PC PC Delayed branch, PC PR, Rm + PC PC Delayed branch, Rm PC Delayed branch, PC PR, Rm PC Delayed branch, PR PC Execution States T Bit 3/1* 3/1* 3/1* 2/1* 2 2 2 2 2 2 2 BF/S label BT label BT/S label BRA label BRAF Rm BSR label BSRF Rm JMP JSR RTS Note: @Rm @Rm One state when the program does not branch. Rev. 4.00 Dec 05, 2005 page 34 of 564 REJ09B0270-0400 Section 2 CPU System Control Instructions Instruction CLRT CLRMAC LDC LDC LDC LDC.L LDC.L LDC.L LDS LDS LDS LDS.L LDS.L LDS.L NOP RTE SETT SLEEP STC STC STC STC.L STC.L STC.L STS STS STS STS.L STS.L SR,Rn GBR,Rn VBR,Rn SR,@-Rn GBR,@-Rn VBR,@-Rn MACH,Rn MACL,Rn PR,Rn MACH,@-Rn MACL,@-Rn Rm,SR Rm,GBR Rm,VBR @Rm+,SR @Rm+,GBR @Rm+,VBR Rm,MACH Rm,MACL Rm,PR @Rm+,MACH @Rm+,MACL @Rm+,PR Instruction Code 0000000000001000 0000000000101000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000001001 0000000000101011 0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0100nnnn00000010 0100nnnn00010010 Operation 0T 0 MACH, MACL Rm SR Rm GBR Rm VBR (Rm) SR, Rm + 4 Rm (Rm) GBR, Rm + 4 Rm (Rm) VBR, Rm + 4 Rm Rm MACH Rm MACL Rm PR (Rm) MACH, Rm + 4 Rm (Rm) MACL, Rm + 4 Rm (Rm) PR, Rm + 4 Rm No operation Delayed branch, stack area PC/SR 1T Sleep SR Rn GBR Rn VBR Rn Rn - 4 Rn, SR (Rn) Rn - 4 Rn, GBR (Rn) Rn - 4 Rn, VBR (Rn) MACH Rn MACL Rn PR Rn Rn - 4 Rn, MACH (Rn) Rn - 4 Rn, MACL (Rn) Execution States T Bit 1 1 1 1 1 3 3 3 1 1 1 1 1 1 1 4 1 3* 1 1 1 2 2 2 1 1 1 1 1 0 LSB LSB 1 Rev. 4.00 Dec 05, 2005 page 35 of 564 REJ09B0270-0400 Section 2 CPU Execution States T Bit 1 8 Instruction STS.L TRAPA Note: * PR,@-Rn #imm Instruction Code 0100nnnn00100010 11000011iiiiiiii Operation Rn - 4 Rn, PR (Rn) PC/SR stack area, (imm x 4 + VBR) PC The number of execution states before the chip enters sleep mode: The execution states shown in the table are minimums. The actual number of states may be increased when (1) contention occurs between instruction fetches and data access, or (2) when the destination register of the load instruction (memory register) equals to the register used by the next instruction. Rev. 4.00 Dec 05, 2005 page 36 of 564 REJ09B0270-0400 Section 2 CPU 2.6 2.6.1 Processing States State Transitions The CPU has four processing states: reset, exception processing, program execution and powerdown. Figure 2.4 shows the transitions between the states. From any state when RES = 0 From any state when RES = 1 and MRES = 0 Power-on reset state RES = 0 Manual reset state RES = 1 RES = 1, MRES = 1 Reset state Exception processing state When an internal power-on reset by WDT or internal manual reset by WDT occurs NMI interrupt or IRQ interrupt occurs Exception processing source occurs Exception processing ends Program execution state SSBY bit set for SLEEP instruction SSBY bit cleared for SLEEP instruction Sleep mode Software standby mode Power-down state Figure 2.4 Transitions between Processing States Rev. 4.00 Dec 05, 2005 page 37 of 564 REJ09B0270-0400 Section 2 CPU Reset State: The CPU resets in the reset state. When the RES pin level goes low, the power-on reset state is entered. When the RES pin is high and the MRES pin is low, the manual reset state is entered. Exception Processing State: The exception processing state is a transient state that occurs when exception processing sources such as resets or interrupts alter the CPU's processing state flow. For a reset, the initial values of the program counter (PC) (execution start address) and stack pointer (SP) are fetched from the exception processing vector table and stored; the CPU then branches to the execution start address and execution of the program begins. For an interrupt, the stack pointer (SP) is accessed and the program counter (PC) and status register (SR) are saved to the stack area. The exception service routine start address is fetched from the exception processing vector table; the CPU then branches to that address and the program starts executing, thereby entering the program execution state. Program Execution State: In the program execution state, the CPU sequentially executes the program. Power-Down State: In the power-down state, the CPU operation halts and power consumption declines. The SLEEP instruction places the CPU in the sleep mode or the software standby mode. Rev. 4.00 Dec 05, 2005 page 38 of 564 REJ09B0270-0400 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Selection of Operating Modes This LSI has one operating modes and four clock modes. The operating mode is determined by the setting of MD3-MD0, and FWP pins. Do not change these pins during LSI operation (while power is on). Do not set these pins in the other way than the combination shown in Table 3.1. Table 3.1 Selection of Operating Modes Pin Setting Mode No. Mode 0* 3 Mode 1* 3 3 Mode 2* FWP 1 1 1 1 0 0 0 0 MD3 x x x x x x x x MD2 x x x x x x x x MD1 0 0 1 1 0 0 1 1 MD0 0 1 0 1 0 1 0 1 Mode Name MCU extension mode 0 MCU extension mode 1 MCU extension mode 2 Single chip mode 2 Boot mode* User programming 2 mode* On-Chip ROM Not Active Not Active Active Active Active Active Mode 3 *3 *2 *3 *2 Notes: The symbol x means "Don't care." 1. Only the mode3 is supported in normal operation in SH7046. 2. User programming mode for flash memory. Supported in only F-ZTAT version. 3. Cannot be used for this LSI. There are two modes as the MCU operating modes: MCU extension mode and single chip mode. There are two modes to program the flash memory (on-board programming mode): boot mode and user programming mode. Rev. 4.00 Dec 05, 2005 page 39 of 564 REJ09B0270-0400 Section 3 MCU Operating Modes The clock mode is selected by the input of MD2 and MD3 pins. Table 3.2 Maximum Operating Clock Frequency for Each Clock Mode Pin Setting MD3 0 0 1 1 Note: * MD2 0 1 0 1 Maximum Operating Clock Frequency 12.5 MHz (Input clock x 1*, maximum of input clock: 12.5 MHz) 25 MHz (Input clock x 2*, maximum of input clock: 12.5 MHz) 40 MHz (Input clock x 4*, maximum of input clock: 10 MHz) 50 MHz (Input clock x 4 for system clock, Input clock x 2 for peripheral clock, maximum of input clock: 12.5 MHz) The frequencies for the system and peripheral module clocks are the same. 3.2 Input/Output Pins Table 3.3 describes the configuration of operating mode related pins. Table 3.3 Pin Name MD0 MD1 MD2 MD3 FWP Operating Mode Pin Configuration Input/Output Input Input Input Input Input Function Designates operating mode through the level applied to this pin Designates operating mode through the level applied to this pin Designates clock mode through the level applied to this pin Designates clock mode through the level applied to this pin Pin for the hardware protection against programming/erasing the on-chip flash memory Rev. 4.00 Dec 05, 2005 page 40 of 564 REJ09B0270-0400 Section 3 MCU Operating Modes 3.3 3.3.1 Explanation of Operating Modes Mode 0 to Mode 2 (MCU extension mode 0 to 2) This mode is not supported in this LSI. 3.3.2 Mode 3 (Single chip mode) All ports can be used in this mode. This LSI supports only this mode. 3.3.3 Clock Mode The input waveform frequency can be used as is, doubled or quadrupled as system clock frequency in mode 0 to mode 3. Rev. 4.00 Dec 05, 2005 page 41 of 564 REJ09B0270-0400 Section 3 MCU Operating Modes 3.4 Address Map The address map for the operating modes are shown in figures 3.1 to 3.3. ROM: 256 kbytes, RAM: 12 kbytes Mode 3 H'00000000 On-chip ROM H'0003FFFF H'FFFF8000 H'FFFFBFFF On-chip peripheral I/O registers H'FFFFD000 On-chip RAM H'FFFFFFFF Figure 3.1 The Address Map of SH7046 Flash Memory Version Rev. 4.00 Dec 05, 2005 page 42 of 564 REJ09B0270-0400 Section 3 MCU Operating Modes ROM: 128kbytes, RAM: 4 kbytes Mode 3 H'00000000 On-chip ROM H'0001FFFF H'FFFF8000 H'FFFFBFFF On-chip peripheral I/O registers H'FFFFF000 On-chip RAM H'FFFFFFFF Figure 3.2 The Address Map of SH7048 Mask ROM Version Rev. 4.00 Dec 05, 2005 page 43 of 564 REJ09B0270-0400 Section 3 MCU Operating Modes ROM: 64 kbytes, RAM: 4 kbytes Mode 3 H'00000000 On-chip ROM H'0000FFFF H'FFFF8000 H'FFFFBFFF On-chip peripheral I/O registers H'FFFFF000 On-chip RAM H'FFFFFFFF Figure 3.3 The Address Map of SH7148 Mask ROM Version Rev. 4.00 Dec 05, 2005 page 44 of 564 REJ09B0270-0400 Section 3 MCU Operating Modes 3.5 Initial State of This LSI In this LSI, some on-chip modules are set to module standby state as its initial state for power down. Therefore, to operate those modules, it is necessary to clear module standby state. For details, refer to section 21, Power-Down Modes. Rev. 4.00 Dec 05, 2005 page 45 of 564 REJ09B0270-0400 Section 3 MCU Operating Modes Rev. 4.00 Dec 05, 2005 page 46 of 564 REJ09B0270-0400 Section 4 Clock Pulse Generator Section 4 Clock Pulse Generator This LSI has an on-chip clock pulse generator (CPG) that generates the system clock () and peripheral clock (P) to generate the internal clock (/2 to /8192, P/2 to P/1024). The CPG consists of an oscillator, PLL circuit, and pre-scaler. A block diagram of the clock pulse generator is shown in figure 4.1. The frequency from the oscillator can be modified by the PLL circuit. PLLCAP EXTAL Oscillator XTAL PLL circuit Clock divider (x 1/2) Pre-scaler MD2 MD3 Pre-scaler Clock mode control circuitry /2 to /8192 P/2 to P/1024 P Within the LSI Figure 4.1 Block Diagram of the Clock Pulse Generator 4.1 Oscillator Clock pulses can be supplied from a connected crystal resonator or an external clock. 4.1.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in figure 4.2. Use the damping resistance (Rd) listed in table 4.1. Use an AT-cut parallel-resonance type crystal resonator that has a resonance frequency of 4-12.5 MHz. It is recommended to consult crystal dealer concerning the compatibility of the crystal resonator and the LSI. CPG0110B_000020020700 Rev. 4.00 Dec 05, 2005 page 47 of 564 REJ09B0270-0400 Section 4 Clock Pulse Generator CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 18-22 pF (Recommended value) Figure 4.2 Connection of the Crystal Resonator (Example) Table 4.1 Damping Resistance Values 4 500 8 200 10 0 12.5 0 Frequency (MHz) Rd () Crystal Resonator: Figure 4.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator with the characteristics listed in table 4.2. CL L XTAL C0 Rs EXTAL AT-cut parallel-resonance type Figure 4.3 Crystal Resonator Equivalent Circuit Table 4.2 Crystal Resonator Characteristics 4 120 7 8 80 7 10 60 7 12.5 50 7 Frequency (MHz) Rs max () C0 max (pF) 4.1.2 External Clock Input Method Figure 4.4 shows an example of an external clock input connection. In this case, make the external clock high level to stop it in standby mode. During operation, make the external input clock frequency 4-12.5 MHz. When leaving the XTAL pin open, make sure the stray capacitance is less than 10 pF. Rev. 4.00 Dec 05, 2005 page 48 of 564 REJ09B0270-0400 Section 4 Clock Pulse Generator Even when inputting an external clock, be sure to wait at least the oscillation stabilization time in power-on sequence or in releasing standby mode, in order to ensure the PLL stabilization time. EXTAL XTAL Open state External clock input Figure 4.4 Example of External Clock Connection 4.2 Function for Detecting the Oscillator Halt This CPG can detect a clock halt and automatically cause the timer pins to become highimpedance when any system abnormality causes the oscillator to halt. That is, when a change of EXTAL has not been detected, the high-current 12 pins (PE9/TIOC3B, PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C, PE15/TIOC4D/IRQOUT, PE16/PUOA/ UBCTRG*, PE17/PVOA, PE18/PWOA, PE19/PUOB, PE20/PVOB, PE21/PWOB) are set to high-impedance regardless of PFC setting. Even in standby mode, these 12 pins become high-impedance regardless of PFC setting. These pins enter the normal state after standby mode is released. When abnormalities that halt the oscillator occur except in standby mode, other LSI operations become undefined. In this case, LSI operations, including these 12 pins, become undefined even when the oscillator operation starts again. Note: * For flash version only 4.3 4.3.1 Usage Notes Note on Crystal Resonator A sufficient evaluation at the user's site is necessary to use the LSI, by referring the resonator connection examples shown in this section, because various characteristics related to the crystal resonator are closely linked to the user's board design. As the resonator circuit constants will depend on the resonator and the floating capacitance of the mounting circuit, the component value should be determined in consultation with the resonator manufacturer. Ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. Rev. 4.00 Dec 05, 2005 page 49 of 564 REJ09B0270-0400 Section 4 Clock Pulse Generator 4.3.2 Notes on Board Design When using a crystal oscillator, place the crystal oscillator and its load capacitors as close as possible to the XTAL and EXTAL pins. Do not route any signal lines near the oscillator circuitry as shown in figure 4.5. Otherwise, correct oscillation can be interfered by induction. Measures against radiation noise are taken in this LSI. If radiation noise needs to be further reduced, usage of a multi-layer printed circuit board with ground planes is recommended. Avoid CL2 Signal A Signal B This LSI XTAL EXTAL CL1 Figure 4.5 Cautions for Oscillator Circuit System Board Design A circuitry shown in figure 4.6 is recommended as an external circuitry around the PLL. Place oscillation stabilization capacitor C1 close to the PLLCAP pin, and ensure that no other signal lines cross this line. Separate PLLVcL and PLLVss circuit against Vcc and Vss circuit from the board power supply source, and be sure to insert bypass capacitors CB and CPB close to the pins. R1: 3k PLLCAP PLLVCL C1: 470 pF CPB = 0.47 F* PLLVSS VCC CB = 0.47 F* VSS (Values are recommended values.) Note: * CB and CPB are laminated ceramic type. Figure 4.6 Recommended External Circuitry Around the PLL Rev. 4.00 Dec 05, 2005 page 50 of 564 REJ09B0270-0400 Section 4 Clock Pulse Generator Electromagnetic waves are radiated from an LSI in operation. This LSI has an electromagnetic peak in the harmonics band whose primary frequency is determined by the lower frequency between the system clock () and peripheral clock (P). For example, when = 50 MHz and P = 40 MHz, the primary frequency is 40 MHz. If this LSI is used adjacent to a device sensitive to electromagnetic interference, e.g. FM/VHF band receiver, a printed circuit board of more than four layers with planes exclusively for system ground is recommended. Rev. 4.00 Dec 05, 2005 page 51 of 564 REJ09B0270-0400 Section 4 Clock Pulse Generator Rev. 4.00 Dec 05, 2005 page 52 of 564 REJ09B0270-0400 Section 5 Exception Processing Section 5 Exception Processing 5.1 5.1.1 Overview Types of Exception Processing and Priority Exception processing is started by four sources: resets, address errors, interrupts and instructions and have the priority, as shown in table 5.1. When several exception processing sources occur at once, they are processed according to the priority. Table 5.1 Exception Reset Address error Interrupt Types of Exception Processing and Priority Source Power-on reset Manual reset CPU address error DTC address error NMI User break IRQ On-chip peripheral modules: Multifunction timer unit (MTU) A/D converter 0 and 1 (A/D0, A/D1) Data transfer controller (DTC) Compare match timer 0 and 1 (CMT0, CMT1) Watchdog timer (WDT) Input/output port (I/O) (MTU) Serial communication interface 2 and 3 (SCI2 and SCI3) * Motor management timer (MMT) * A/D converter 2 (A/D2) * Input/output port (I/O) (MMT) Trap instruction (TRAPA instruction) Low * * * * * * * Priority High Instructions General illegal instructions (undefined code) Illegal slot instructions (undefined code placed directly after a delay 1 2 branch instruction* or instructions that rewrite the PC* ) Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and BRAF. 2. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, and BRAF. Rev. 4.00 Dec 05, 2005 page 53 of 564 REJ09B0270-0400 Section 5 Exception Processing 5.1.2 Exception Processing Operations The exception processing sources are detected and the processing starts according to the timing shown in table 5.2. Table 5.2 Exception Reset Timing for Exception Source Detection and Start of Exception Processing Source Power-on reset Manual reset Timing of Source Detection and Start of Processing Starts when the RES pin changes from low to high or when WDT overflows. Starts when the MRES pin changes from low to high. Detected when instruction is decoded and starts when the execution of the previous instruction is completed. Trap instruction General illegal instructions Illegal slot instructions Starts from the execution of a TRAPA instruction. Starts from the decoding of undefined code anytime except after a delayed branch instruction (delay slot). Starts from the decoding of undefined code placed in a delayed branch instruction (delay slot) or of instructions that rewrite the PC. Address error Interrupts Instructions When exception processing starts, the CPU operates as follows: 1. Exception processing triggered by reset: The initial values of the program counter (PC) and stack pointer (SP) are fetched from the exception processing vector table (PC and SP are respectively the H'00000000 and H'00000004 addresses for power-on resets and the H'00000008 and H'0000000C addresses for manual resets). See section 5.1.3, Exception Processing Vector Table, for more information. H'00000000 is then written to the vector base register (VBR) , and H'F (B'1111) is written to the interrupt mask bits (I3 to I0) of the status register (SR). The program begins running from the PC address fetched from the exception processing vector table. 2. Exception processing triggered by address errors, interrupts and instructions: SR and PC are saved to the stack indicated by R15. For interrupt exception processing, the interrupt priority level is written to the SR's interrupt mask bits (I3 to I0). For address error and instruction exception processing, the I3 to I0 bits are not affected. The start address is then fetched from the exception processing vector table and the program begins running from that address. Rev. 4.00 Dec 05, 2005 page 54 of 564 REJ09B0270-0400 Section 5 Exception Processing 5.1.3 Exception Processing Vector Table Before exception processing begins running, the exception processing vector table must be set in memory. The exception processing vector table stores the start addresses of exception service routines. (The reset exception processing table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets. The vector table addresses are calculated from these vector numbers and vector table address offsets. During exception processing, the start addresses of the exception service routines are fetched from the exception processing vector table that is indicated by this vector table address. Table 5.3 shows the vector numbers and vector table address offsets. Table 5.4 shows how vector table addresses are calculated. Table 5.3 Exception Processing Vector Table Vector Numbers PC SP Manual reset PC SP General illegal instruction (Reserved by system) Slot illegal instruction (Reserved by system) CPU address error DTC address error Interrupts (Reserved by system) NMI User break 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 : 31 Vector Table Address Offset H'00000000-H'00000003 H'00000004-H'00000007 H'00000008-H'0000000B H'0000000C-H'0000000F H'00000010-H'00000013 H'00000014-H'00000017 H'00000018-H'0000001B H'0000001C-H'0000001F H'00000020-H'00000023 H'00000024-H'00000027 H'00000028-H'0000002B H'0000002C-H'0000002F H'00000030-H'00000033 H'00000034-H'00000037 H'00000038-H'0000003B H'0000003C-H'0000003F : H'0000007C-H'0000007F Exception Sources Power-on reset Rev. 4.00 Dec 05, 2005 page 55 of 564 REJ09B0270-0400 Section 5 Exception Processing Exception Sources Trap instruction (user vector) Vector Numbers 32 : 63 Interrupts IRQ0 IRQ1 IRQ2 IRQ3 Reserved by system Reserved by system Reserved by system Reserved by system On-chip peripheral module* 64 65 66 67 68 69 70 71 72 : 255 Note: * Vector Table Address Offset H'00000080-H'00000083 : H'000000FC-H'000000FF H'00000100-H'00000103 H'00000104-H'00000107 H'00000108-H'0000010B H'0000010C-H'0000010F H'00000110-H'00000113 H'00000114-H'00000117 H'00000118-H'0000011B H'0000011C-H'0000011F H'00000120-H'00000123 : H'000003FC-H'000003FF The vector numbers and vector table address offsets for each on-chip peripheral module interrupt are given in section 6, Interrupt Controller, and table 6.2, Interrupt Exception Sources, Vector Addresses and Priorities. Table 5.4 Calculating Exception Processing Vector Table Addresses Vector Table Address Calculation Vector table address = (vector table address offset) = (vector number) x 4 Vector table address = VBR + (vector table address offset) = VBR + (vector number) x 4 Exception Source Resets Address errors, interrupts, instructions Notes: 1. VBR: Vector base register 2. Vector table address offset: See table 5.3. 3. Vector number: See table 5.3. Rev. 4.00 Dec 05, 2005 page 56 of 564 REJ09B0270-0400 Section 5 Exception Processing 5.2 5.2.1 Resets Types of Reset Resets have the highest priority of any exception source. There are two types of resets: manual resets and power-on resets. As table 5.5 shows, both types of resets initialize the internal status of the CPU. In power-on resets, all registers of the on-chip peripheral modules are initialized; in manual resets, they are not. Table 5.5 Reset Status Conditions for Transition to Reset Status WDT Overflow Overflow Internal Status On-Chip Peripheral Module Initialized Initialized Not initialized Type Power-on reset Manual reset RES Low High High MRES High Low CPU/INTC Initialized Initialized Initialized PFC, IO Port Initialized Not initialized Not initialized 5.2.2 Power-On Reset Power-On Reset by RES Pin: When the RES pin is driven low, the LSI becomes to be a poweron reset state. To reliably reset the LSI, the RES pin should be kept at low for at least the duration of the oscillation settling time when applying power or when in standby mode (when the clock circuit is halted) or at least 20 tcyc when the clock circuit is running. During power-on reset, CPU internal status and all registers of on-chip peripheral modules are initialized. See Appendix B, Pin States, for the status of individual pins during the power-on reset status. In the power-on reset status, power-on reset exception processing starts when the RES pin is first driven low for a set period of time and then returned to high. The CPU will then operate as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception processing vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3 to I0) of the status register (SR) are set to H'F (B'1111). Rev. 4.00 Dec 05, 2005 page 57 of 564 REJ09B0270-0400 Section 5 Exception Processing 4. The values fetched from the exception processing vector table are set in PC and SP, then the program begins executing. Be certain to always perform power-on reset processing when turning the system power on. Power-On Reset by WDT: When a setting is made for a power-on reset to be generated in the WDT's watchdog timer mode, and the WDT's TCNT overflows, the LSI becomes to be a poweron reset state. The pin function controller (PFC) registers and I/O port registers are not initialized by the reset signal generated by the WDT (these registers are initialized only by a power-on reset from outside of the chip). If reset caused by the input signal at the RES pin and a reset caused by WDT overflow occur simultaneously, the RES pin reset has priority, and the WOVF bit in RSTCSR is cleared to 0. When WDT-initiated power-on reset processing is started, the CPU operates as follows: 1. The initial value (execution start address) of the program counter (PC) is fetched from the exception processing vector table. 2. The initial value of the stack pointer (SP) is fetched from the exception processing vector table. 3. The vector base register (VBR) is cleared to H'00000000 and the interrupt mask bits (I3-I0) of the status register (SR) are set to H'F (B'1111). 4. The values fetched from the exception processing vector table are set in the PC and SP, then the program begins executing. 5.2.3 Manual Reset When the RES pin is high and the MRES pin is driven low, the LSI enters a manual reset state. To reliably reset the LSI, the MRES pin should be kept at low for at least the duration of the oscillation settling time that is set in WDT in standby mode (when the clock is halted) or at least 20 tcyc when the clock is operating. During manual reset, the CPU internal status is initialized. Registers of on-chip peripheral modules are not initialized. When the LSI enters manual reset status in the middle of a bus cycle, manual reset exception processing does not start until the bus cycle has ended. Thus, manual resets do not abort bus cycles. However, once MRES is driven low, hold the low level until the CPU becomes to be a manual reset mode after the bus cycle ends. (Keep at low level for at least the longest bus cycle). See Appendix B, Pin States, for the status of individual pins during manual reset mode. In the manual reset status, manual reset exception processing starts when the MRES pin is first kept low for a set period of time and then returned to high. The CPU will then operate in the same procedures as described for power-on resets. Rev. 4.00 Dec 05, 2005 page 58 of 564 REJ09B0270-0400 Section 5 Exception Processing 5.3 5.3.1 Address Errors The Cause of Address Error Exception Address errors occur when instructions are fetched or data is read or written, as shown in table 5.6. Table 5.6 Bus Cycles and Address Errors Bus Cycle Type Instruction fetch Bus Master CPU Bus Cycle Description Instruction fetched from even address Instruction fetched from odd address Instruction fetched from other than on-chip peripheral module space* Instruction fetched from on-chip peripheral module space* Instruction fetched from external memory space when in single chip mode Data read/write CPU or DTC Word data accessed from even address Word data accessed from odd address Longword data accessed from a longword boundary Longword data accessed from other than a long-word boundary Byte or word data accessed in on-chip peripheral module space* Longword data accessed in 16-bit on-chip peripheral module space* Longword data accessed in 8-bit on-chip peripheral module space* External memory space accessed when in single chip mode Note: * Address Errors None (normal) Address error occurs None (normal) Address error occurs Address error occurs None (normal) Address error occurs None (normal) Address error occurs None (normal) None (normal) Address error occurs Address error occurs See section 9, Bus State Controller (BSC) for more information on the on-chip peripheral module space. Rev. 4.00 Dec 05, 2005 page 59 of 564 REJ09B0270-0400 Section 5 Exception Processing 5.3.2 Address Error Exception Processing When an address error occurs, the bus cycle in which the address error occurred ends, the current instruction finishes, and then address error exception processing starts. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the last executed instruction. 3. The start address of the exception service routine is fetched from the exception processing vector table that corresponds to the occurred address error, and the program starts executing from that address. The jump in this case is not a delayed branch. 5.4 5.4.1 Interrupts Interrupt Sources Table 5.7 shows the sources that start the interrupt exception processing. They are NMI, user breaks, IRQ and on-chip peripheral modules. Table 5.7 Type NMI User break IRQ On-chip peripheral module Interrupt Sources Request Source NMI pin (external input) User break controller IRQ0-IRQ3 pins (external input) Multifunction timer unit Data transfer controller Compare match timer A/D converter (A/D0 and A/D1) A/D converter (A/D2) Serial communication interface Watchdog timer Motor management timer Input/output Port 1 1 4 23 1 2 2 1 8 1 2 2 Number of Sources Rev. 4.00 Dec 05, 2005 page 60 of 564 REJ09B0270-0400 Section 5 Exception Processing Each interrupt source is allocated a different vector number and vector table offset. See section 6, Interrupt Controller (INTC), and table 6.2, Interrupt Exception Sources, Vector Addresses and Priorities, for more information on vector numbers and vector table address offsets. 5.4.2 Interrupt Priority Level The interrupt priority is predetermined. When multiple interrupts occur simultaneously (overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and starts the exception processing according to the results. The priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always accepted. The priority level of the user break interrupt is 15. IRQ interrupt and on-chip peripheral module interrupt priority levels can be set freely using the INTC's interrupt priority registers A, D to K (IPRA, IPRD to IPRK) as shown in table 5.8. The priority levels that can be set are 0 to 15. Level 16 cannot be set. See section 6.3.4, Interrupt Priority Registers A, D to K (IPRA, IPRD to IPRK), for more information on IPRA to IPRK. Table 5.8 Type NMI User break IRQ On-chip peripheral module Interrupt Priority Priority Level 16 15 0-15 Comment Fixed priority level. Cannot be masked. Fixed priority level. Set with interrupt priority registers A through K (IPRA-IPRK). 5.4.3 Interrupt Exception Processing When an interrupt occurs, the interrupt controller (INTC) ascertains its priority level. NMI is always accepted, but other interrupts are only accepted if they have a priority level higher than the priority level set in the interrupt mask bits (I3 to I0) of the status register (SR). When an interrupt is accepted, exception processing begins. In interrupt exception processing, the CPU saves SR and the program counter (PC) to the stack. The priority level value of the accepted interrupt is written to SR bits I3 to I0. For NMI, however, the priority level is 16, but the value set in I3 to I0 is H'F (level 15). Next, the start address of the exception service routine is fetched from the exception processing vector table for the accepted interrupt, that address is jumped to and execution begins. See section 6.6, Interrupt Operation, for more information on the interrupt exception processing. Rev. 4.00 Dec 05, 2005 page 61 of 564 REJ09B0270-0400 Section 5 Exception Processing 5.5 5.5.1 Exceptions Triggered by Instructions Types of Exceptions Triggered by Instructions Exception processing can be triggered by trap instruction, illegal slot instructions, and general illegal instructions, as shown in table 5.9. Table 5.9 Type Trap instruction Illegal slot instructions Types of Exceptions Triggered by Instructions Source Instruction TRAPA Undefined code placed immediately after a delayed branch instruction (delay slot) or instructions that rewrite the PC Comment Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, BRAF Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA, BF/S, BT/S, BSRF, BRAF General illegal instructions Undefined code anywhere besides in a delay slot 5.5.2 Trap Instructions When a TRAPA instruction is executed, trap instruction exception processing starts. The CPU operates as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the instruction to be executed after the TRAPA instruction. 3. The CPU reads the start address of the exception service routine from the exception processing vector table that corresponds to the vector number specified in the TRAPA instruction, jumps to that address and starts excuting the program. This jump is not a delayed branch. Rev. 4.00 Dec 05, 2005 page 62 of 564 REJ09B0270-0400 Section 5 Exception Processing 5.5.3 Illegal Slot Instructions An instruction placed immediately after a delayed branch instruction is called "instruction placed in a delay slot". When the instruction placed in the delay slot is an undefined code, illegal slot exception processing starts after the undefined code is decoded. Illegal slot exception processing also starts when an instruction that rewrites the program counter (PC) is placed in a delay slot and the instruction is decoded. The CPU handles an illegal slot instruction as follows: 1. The status register (SR) is saved to the stack. 2. The program counter (PC) is saved to the stack. The PC value saved is the target address of the delayed branch instruction immediately before the undefined code or the instruction that rewrites the PC. 3. The start address of the exception service routine is fetched from the exception processing vector table that corresponds to the exception that occurred. That address is jumped to and the program starts executing. The jump in this case is not a delayed branch. 5.5.4 General Illegal Instructions When undefined code placed anywhere other than immediately after a delayed branch instruction (i.e., in a delay slot) is decoded, general illegal instruction exception processing starts. The CPU handles the general illegal instructions in the same procedures as in the illegal slot instructions. Unlike processing of illegal slot instructions, however, the program counter value that is stacked is the start address of the undefined code. Rev. 4.00 Dec 05, 2005 page 63 of 564 REJ09B0270-0400 Section 5 Exception Processing 5.6 Cases when Exception Sources Are Not Accepted When an address error or interrupt is generated directly after a delayed branch instruction or interrupt-disabled instruction, it is sometimes not accepted immediately but stored instead, as shown in table 5.10. In this case, it will be accepted when an instruction that can accept the exception is decoded. Table 5.10 Generation of Exception Sources Immediately after a Delayed Branch Instruction or Interrupt-Disabled Instruction Exception Source Point of Occurrence Immediately after a delayed branch instruction* 1 2 Address Error Not accepted Accepted Interrupt Not accepted Not accepted Immediately after an interrupt-disabled instruction* Notes: 1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and BRAF 2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, and STS.L 5.6.1 Immediately after a Delayed Branch Instruction When an instruction placed immediately after a delayed branch instruction (delay slot) is decoded, neither address errors nor interrupts are accepted. The delayed branch instruction and the instruction placed immediately after it (delay slot) are always executed consecutively, so no exception processing occurs during this period. 5.6.2 Immediately after an Interrupt-Disabled Instruction When an instruction placed immediately after an interrupt-disabled instruction is decoded, interrupts are not accepted. Address errors can be accepted. Rev. 4.00 Dec 05, 2005 page 64 of 564 REJ09B0270-0400 Section 5 Exception Processing 5.7 Stack Status after Exception Processing Ends The status of the stack after exception processing ends is shown in table 5.11. Table 5.11 Stack Status after Exception Processing Ends Types Address error SP Address of instruction 32 bits after executed instruction SR 32 bits Stack Status Trap instruction SP Address of instruction after TRAPA instruction SR 32 bits 32 bits General illegal instruction SP Address of instruction after general illegal instruction 32 bits SR 32 bits Interrupt SP Address of instruction after executed instruction 32 bits SR 32 bits Illegal slot instruction SP Jump destination address of delay branch instruction 32 bits SR 32 bits Rev. 4.00 Dec 05, 2005 page 65 of 564 REJ09B0270-0400 Section 5 Exception Processing 5.8 5.8.1 Usage Notes Value of Stack Pointer (SP) The value of the stack pointer must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 5.8.2 Value of Vector Base Register (VBR) The value of the vector base register must always be a multiple of four. If it is not, an address error will occur when the stack is accessed during exception processing. 5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing When the value of the stack pointer is not a multiple of four, an address error will occur during stacking of the exception processing (interrupts, etc.) and address error exception processing will start after the first exception processing is ended. Address errors will also occur in the stacking for this address error exception processing. To ensure that address error exception processing does not go into an endless loop, no address errors are accepted at that point. This allows program control to be shifted to the service routine for address error exception and enables error processing. When an address error occurs during exception processing stacking, the stacking bus cycle (write) is executed. During stacking of the status register (SR) and program counter (PC), the value of SP is reduced by 4 for both of SR and PC, therefore the value of SP is still not a multiple of four after the stacking. The address value output during stacking is the SP value, so the address itself where the error occurred is output. This means that the write data stacked is undefined. Rev. 4.00 Dec 05, 2005 page 66 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. 6.1 Features * 16 levels of interrupt priority * NMI noise canceler function * Occurrence of interrupt can be reported externally (IRQOUT pin) Figure 6.1 shows a block diagram of the INTC. Rev. 4.00 Dec 05, 2005 page 67 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) IRQOUT NMI IRQ0 IRQ1 IRQ2 IRQ3 UBC DTC MTU CMT MMT A/D SCI WDT I/O Input control CPU/DTC request determination Priority determination Comparator Interrupt request SR I3 I2 I1 I0 CPU (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) DTER ICR1 ICR2 ISR IPRA to IPRK Internal bus IPR DTC Module bus Bus interface INTC Legend: UBC: User break controller DTC: Data transfer controller MTU: Multifunction timer unit CMT: Compare match timer MMT: Motor management timer A/D: A/D converter SCI: WDT: I/O: ICR1, ICR2: ISR: IPRA to IPRK: SR: Serial communications interface Watchdog timer I/O port (Port output controller) Interrupt control register IRQ status register Interrupt priority level setting registers A to K Status register Figure 6.1 INTC Block Diagram Rev. 4.00 Dec 05, 2005 page 68 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) 6.2 Input/Output Pins Table 6.1 shows the INTC pin configuration. Table 6.1 Name Non-maskable interrupt input pin Interrupt request input pins Interrupt request output pin Pin Configuration Abbreviation NMI IRQ0-IRQ3 IRQOUT I/O I I O Function Input of non-maskable interrupt request signal Input of maskable interrupt request signals Output of notification signal when an interrupt has occurred 6.3 Register Descriptions The interrupt controller has the following registers. For details on register addresses and register states during each processing, refer to appendix A, Internal I/O Register. * Interrupt control register 1 (ICR1) * Interrupt control register 2 (ICR2) * IRQ status register (ISR) * Interrupt priority register A (IPRA) * Interrupt priority register D (IPRD) * Interrupt priority register E (IPRE) * Interrupt priority register F (IPRF) * Interrupt priority register G (IPRG) * Interrupt priority register H (IPRH) * Interrupt priority register I (IPRI) * Interrupt priority register J (IPRJ) * Interrupt priority register K (IPRK) Rev. 4.00 Dec 05, 2005 page 69 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) 6.3.1 Interrupt Control Register 1 (ICR1) ICR1 is a 16-bit register that sets the input signal detection mode of the external interrupt input pins NMI and IRQ0 to IRQ3 and indicates the input signal level at the NMI pin. Bit 15 Bit Name NMIL Initial Value 1/0 R/W R Description NMI Input Level Sets the level of the signal input to the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified. 0: NMI input level is low 1: NMI input level is high 14 to 9 8 All 0 R Reserved These bits are always read as 0. The write value should always be 0. NMIE 0 R/W NMI Edge Select 0: Interrupt request is detected on falling edge of NMI input 1: Interrupt request is detected on rising edge of NMI input 7 IRQ0S 0 R/W IRQ0 Sense Select This bit sets the IRQ0 interrupt request detection mode. 0: Interrupt request is detected on low level of IRQ0 input 1: Interrupt request is detected on edge of IRQ0 input (edge direction is selected by ICR2) 6 IRQ1S 0 R/W IRQ1 Sense Select This bit sets the IRQ1 interrupt request detection mode. 0: Interrupt request is detected on low level of IRQ1 input 1: Interrupt request is detected on edge of IRQ1 input (edge direction is selected by ICR2) Rev. 4.00 Dec 05, 2005 page 70 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) Initial Value 0 Bit 5 Bit Name IRQ2S R/W R/W Description IRQ2 Sense Select This bit sets the IRQ2 interrupt request detection mode. 0: Interrupt request is detected on low level of IRQ2 input 1: Interrupt request is detected on edge of IRQ2 input (edge direction is selected by ICR2) 4 IRQ3S 0 R/W IRQ3 Sense Select This bit sets the IRQ3 interrupt request detection mode. 0: Interrupt request is detected on low level of IRQ3 input 1: Interrupt request is detected on edge of IRQ3 input (edge direction is selected by ICR2) 3 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 6.3.2 Interrupt Control Register 2 (ICR2) ICR2 is a 16-bit register that sets the edge detection mode of the external interrupt input pins IRQ0 to IRQ3. ICR2 is, however, valid only when IRQ interrupt request detection mode is set to the edge detection mode by the sense select bits of IRQ0 to IRQ 3 in Interrupt control register 1 (ICR1). If the IRQ interrupt request detection mode has been set to low level detection mode, the setting of ICR2 is ignored. Bit 15 14 Bit Name IRQ0ES1 IRQ0ES0 Initial Value 0 0 R/W R/W R/W Description This bit sets the IRQ0 interrupt request edge detection mode. 00: Interrupt request is detected on falling edge of IRQ0 input 01: Interrupt request is detected on rising edge of IRQ0 input 10: Interrupt request is detected on both of falling and rising edge of IRQ0 input 11: Cannot be set Rev. 4.00 Dec 05, 2005 page 71 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) Initial Value 0 0 Bit 13 12 Bit Name IRQ1ES1 IRQ1ES0 R/W R/W R/W Description This bit sets the IRQ1 interrupt request edge detection mode. 00: Interrupt request is detected on falling edge of IRQ1 input 01: Interrupt request is detected on rising edge of IRQ1 input 10: Interrupt request is detected on both of falling and rising edge of IRQ1 input 11: Cannot be set 11 10 IRQ2ES1 IRQ2ES0 0 0 R/W R/W This bit sets the IRQ2 interrupt request edge detection mode. 00: Interrupt request is detected on falling edge of IRQ2 input 01: Interrupt request is detected on rising edge of IRQ2 input 10: Interrupt request is detected on both of falling and rising edge of IRQ2 input 11: Cannot be set 9 8 IRQ3ES1 IRQ3ES0 0 0 R/W R/W This bit sets the IRQ3 interrupt request edge detection mode. 00: Interrupt request is detected on falling edge of IRQ3 input 01: Interrupt request is detected on rising edge of IRQ3 input 10: Interrupt request is detected on both of falling and rising edge of IRQ3 input 11: Cannot be set 7 to 0 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Dec 05, 2005 page 72 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) 6.3.3 IRQ Status Register (ISR) ISR is a 16-bit register that indicates the interrupt request status of the external interrupt input pins IRQ0 to IRQ3. When IRQ interrupts are set to edge detection, held interrupt requests can be withdrawn by writing 0 to IRQnF after reading IRQnF = 1. Bit 15 to 8 7 6 5 4 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. IRQ0F IRQ1F IRQ2F IRQ3F 0 0 0 0 R/W R/W R/W R/W IRQ0 to IRQ3 Flags These bits display the IRQ0 to IRQ3 interrupt request status. [Setting condition] * When interrupt source that is selected by ICR1 and ICR2 has occurred. When 0 is written after reading IRQnF = 1 When interrupt exception processing has been executed at high level of IRQn input under the low level detection mode. When IRQn interrupt exception processing has been executed under the edge detection mode of falling edge, rising edge or both of falling and rising edge. When the DISEL bit of DTMR of DTC is 0, after DTC has been started by IRQn interrupt. [Clearing conditions] * * * * 3 to 0 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Dec 05, 2005 page 73 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) 6.3.4 Interrupt Priority Registers A, D to K (IPRA, IPRD to IPRK) Interrupt priority registers are nine 16-bit readable/writable registers that set priority levels from 0 to 15 for interrupts except NMI. For the correspondence between interrupt request sources and IPR, refer to table 6.2 Interrupt Request Sources, Vector Address, and Interrupt Priority Level. Each of the corresponding interrupt priority ranks are established by setting a value from H'0 to H'F in each of the four-bit groups 15 to 12, 11 to 8, 7 to 4 and 3 to 0. Reserved bits that are not assigned should be set H'0 (B'0000.) Bit 15 14 13 12 Bit Name IPR15 IPR14 IPR13 IPR12 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description These bits set priority levels for the corresponding interrupt source. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Priority level 0 (lowest) Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 Priority level 7 Priority level 8 Priority level 9 Priority level 10 Priority level 11 Priority level 12 Priority level 13 Priority level 14 Priority level 15 (highest) Rev. 4.00 Dec 05, 2005 page 74 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) Initial Value 0 0 0 0 Bit 11 10 9 8 Bit Name IPR11 IPR10 IPR9 IPR8 R/W R/W R/W R/W R/W Description These bits set priority levels for the corresponding interrupt source. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Priority level 0 (lowest) Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 Priority level 7 Priority level 8 Priority level 9 Priority level 10 Priority level 11 Priority level 12 Priority level 13 Priority level 14 Priority level 15 (highest) 7 6 5 4 IPR7 IPR6 IPR5 IPR4 0 0 0 0 R/W R/W R/W R/W These bits set priority levels for the corresponding interrupt source. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Priority level 0 (lowest) Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 Priority level 7 Priority level 8 Priority level 9 Priority level 10 Priority level 11 Priority level 12 Priority level 13 Priority level 14 Priority level 15 (highest) Rev. 4.00 Dec 05, 2005 page 75 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) Initial Value 0 0 0 0 Bit 3 2 1 0 Bit Name IPR3 IPR2 IPR1 IPR0 R/W R/W R/W R/W R/W Description These bits set priority levels for the corresponding interrupt source. 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Priority level 0 (lowest) Priority level 1 Priority level 2 Priority level 3 Priority level 4 Priority level 5 Priority level 6 Priority level 7 Priority level 8 Priority level 9 Priority level 10 Priority level 11 Priority level 12 Priority level 13 Priority level 14 Priority level 15 (highest) Note: Name in the tables above is represented by a general name. Name in the list of register is, on the other hand, represented by a module name. Rev. 4.00 Dec 05, 2005 page 76 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) 6.4 6.4.1 Interrupt Sources External Interrupts There are four types of interrupt sources: NMI, user breaks, IRQ, and on-chip peripheral modules. Each interrupt has a priority expressed as a priority level (0 to 16, with 0 the lowest and 16 the highest). Giving an interrupt a priority level of 0 masks it. NMI Interrupts: The NMI interrupt has priority 16 and is always accepted. Input at the NMI pin is detected by edge. Use the NMI edge select bit (NMIE) in the interrupt control register 1 (ICR1) to select either the rising or falling edge. NMI interrupt exception processing sets the interrupt mask level bits (I3-I0) in the status register (SR) to level 15. IRQ3 to IRQ0 Interrupts: IRQ interrupts are requested by input from pins IRQ0-IRQ3. Set the IRQ sense select bits (IRQ0S-IRQ3S) of the interrupt control register 1 (ICR1) and IRQ edge select bit (IRQ0ES[1:0]-IRQ3ES[1:0]) of the interrupt control register 2 (ICR2) to select low level detection, falling edge detection, or rising edge detection for each pin. The priority level can be set from 0 to 15 for each pin using the interrupt priority registers A (IPRA). When IRQ interrupts are set to low level detection, an interrupt request signal is sent to the INTC during the period the IRQ pin is low level. Interrupt request signals are not sent to the INTC when the IRQ pin becomes high level. Interrupt request levels can be confirmed by reading the IRQ flags (IRQ0F-IRQ3F) of the IRQ status register (ISR). When IRQ interrupts are set to falling edge detection, interrupt request signals are sent to the INTC upon detecting a change on the IRQ pin from high to low level. The results of detection for IRQ interrupt request are maintained until the interrupt request is accepted. It is possible to confirm that IRQ interrupt requests have been detected by reading the IRQ flags (IRQ0F-IRQ3F) of the IRQ status register (ISR), and by writing a 0 after reading a 1, IRQ interrupt request detection results can be withdrawn. In IRQ interrupt exception processing, the interrupt mask bits (I3-I0) of the status register (SR) are set to the priority level value of the accepted IRQ interrupt. Figure 6.2 shows the block diagram of this IRQ3 to IRQ0 interrupts. Rev. 4.00 Dec 05, 2005 page 77 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) IRQnS IRQnES ISR.IRQnF DTC Selection IRQ pins Level detection Edge detection S Q determination CPU interrupt request RESIRQn R DTC starting request (Acceptance of IRQn interrupt/DTC transfer end/ writing 0 after reading IRQnF = 1) Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control 6.4.2 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral modules. As a different interrupt vector is assigned to each interrupt source, the exception service routine does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be assigned to individual on-chip peripheral modules in interrupt priority registers A, D to K (IPRA, IPRD to IPRK). On-chip peripheral module interrupt exception processing sets the interrupt mask level bits (I3-I0) in the status register (SR) to the priority level value of the on-chip peripheral module interrupt that was accepted. 6.4.3 User Break Interrupt A user break interrupt has a priority of level 15, and occurs when the break condition set in the user break controller (UBC) is satisfied. User break interrupt requests are detected by edge and are held until accepted. User break interrupt exception processing sets the interrupt mask level bits (I3-I0) in the status register (SR) to level 15. For more details about the user break interrupt, see Section 7, User Break Controller (UBC). Rev. 4.00 Dec 05, 2005 page 78 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) 6.5 Interrupt Exception Processing Vectors Table Table 6.2 lists interrupt sources and their vector numbers, vector table address offsets and interrupt priorities. Each interrupt source is allocated a different vector number and vector table address offset. Vector table addresses are calculated from the vector numbers and address offsets. In interrupt exception processing, the exception service routine start address is fetched from the vector table indicated by the vector table address. For the details of calculation of vector table address, see table 5.4, Calculating Exception Processing Vector Table Addresses in the section 5 Exception Processing. IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and 15 for each pin or module by setting interrupt priority registers A-K (IPRA-IPRK). However, the smaller vector number has interrupt source, the higher priority ranking is assigned among two or more interrupt sources specified by the same IPR, and the priority ranking cannot be changed. A power-on reset assigns priority level 0 to IRQ interrupts and on-chip peripheral module interrupts. If the same priority level is assigned to two or more interrupt sources and interrupts from those sources occur simultaneously, they are processed by the default priority order indicated in table 6.2. Rev. 4.00 Dec 05, 2005 page 79 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) Table 6.2 Interrupt Source External pin User break Interrupts Interrupt Exception Processing Vectors and Priorities Name NMI Reserved by system Reserved by system IRQ0 IRQ1 IRQ2 IRQ3 Reserved by system Reserved by system Reserved by system Reserved by system Vector No. 11 12 14 15 64 65 66 67 68 69 70 71 72 76 80 84 88 89 90 91 92 96 97 100 101 104 105 108 109 Vector Table Starting Address IPR H'0000002C H'00000030 H'00000038 H'0000003C H'00000100 H'00000104 H'00000108 H'0000010C H'00000110 H'00000114 H'00000118 H'0000011C H'00000120 H'00000130 H'00000140 H'00000150 H'00000160 H'00000164 H'00000168 H'0000016C H'00000170 H'00000180 H'00000184 H'00000190 H'00000194 H'000001A0 H'000001A4 H'000001B0 H'000001B4 IPRE11-IPRE8 Low IPRE15-IPRE12 IPRD3-IPRD0 IPRD11-IPRD8 IPRD7-IPRD4 IPRA15-IPRA12 IPRA11-IPRA8 IPRA7-IPRA4 IPRA3-IPRA0 IPRD15-IPRD12 Default Priority High Reserved by system Reserved by system Reserved by system Reserved by system MTU channel 0 TGIA_0 TGIB_0 TGIC_0 TGID_0 TCIV_0 MTU channel 1 TGIA_1 TGIB_1 TCIV_1 TCIU_1 MTU channel 2 TGIA_2 TGIB_2 TCIV_2 TCIU_2 Rev. 4.00 Dec 05, 2005 page 80 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) Interrupt Source Vector No. 112 113 114 115 116 120 121 122 123 124 Vector Table Starting Address IPR H'000001C0 H'000001C4 H'000001C8 H'000001CC H'000001D0 H'000001E0 H'000001E4 H'000001E8 H'000001EC H'000001F0 IPRF11-IPRF8 IPRG15-IPRG12 IPRG11-IPRG8 IPRG7-IPRG4 IPRG3-IPRG0 IPRH15-IPRH12 IPRH11-IPRH8 IPRI15-IPRI12 IPRE3-IPRE0 IPRF15-IPRF12 IPRE7-IPRE4 Default Priority High Name MTU channel 3 TGIA_3 TGIB_3 TGIC_3 TGID_3 TCIV_3 MTU channel 4 TGIA_4 TGIB_4 TGIC_4 TGID_4 TCIV_4 A/D DTC CMT Watchdog timer I/O (MTU) SCI channel 2 Reserved by system ADI0 ADI1 SWDTEND CMI0 CMI1 ITI Reserved by system MTUPOE Reserved by system ERI_2 RXI_2 TXI_2 TEI_2 SCI channel 3 ERI_3 RXI_3 TXI_3 TEI_3 Reserved by system 128-135 H'00000200- H'0000021C 136 137 140 144 148 152 153 156 H'00000220 H'00000224 H'00000230 H'00000240 H'00000250 H'00000260 H'00000264 H'00000270 160-167 H'00000290- H'0000029C 168 169 170 171 172 173 174 175 H'000002A0 H'000002A4 H'000002A8 H'000002AC H'000002B0 H'000002B4 H'000002B8 H'000002BC IPRI11-IPRI8 176-179 H'000002C0- H'000002CC Low Rev. 4.00 Dec 05, 2005 page 81 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) Interrupt Source MMT A/D2 I/O (MMT) Vector No. 180 181 184 Vector Table Starting Address IPR H'000002D0 H'000002D4 H'000002E0 IPRJ15-IPRJ12 IPRK15-IPRK12 Low IPRI3-IPRI0 Default Priority High Name TGIM TGIN ADI2 Reserved by system MMTPOE Reserved by system 188-196 H'000002F0- H'00000310 200 H'00000320 204-212 H'00000330- H'000003DC 6.6 6.6.1 Interrupt Operation Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent, according to the priority levels set in interrupt priority level setting registers A-K (IPRA- IPRK). Interrupts that have lower-priority than that of the selected interrupt are ignored.* If interrupts that have the same priority level or interrupts within a same module occur simultaneously, the interrupt with the highest priority is selected according to the default priority order indicated in table 6.2. 3. The interrupt controller compares the priority level of the selected interrupt request with the interrupt mask bits (I3-I0) in the CPU's status register (SR). If the request priority level is equal to or less than the level set in I3-I0, the request is ignored. If the request priority level is higher than the level in bits I3-I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. 4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin. 5. The CPU detects the interrupt request sent from the interrupt controller when CPU decodes the instruction to be executed. Instead of executing the decoded instruction, the CPU starts interrupt exception processing (figure 6.5). 6. SR and PC are saved onto the stack. 7. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3-I0) in the status register (SR). Rev. 4.00 Dec 05, 2005 page 82 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) 8. When the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high level is output from the IRQOUT pin. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when the CPU starts interrupt exception processing instead of instruction execution as noted in (5) above. However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepting, the IRQOUT pin holds low level. 9. The CPU reads the start address of the exception service routine from the exception vector table for the accepted interrupt, jumps to that address, and starts executing the program. This jump is not a delay branch. Note: * Interrupt requests that are designated as edge-detect type are held pending until the interrupt requests are accepted. IRQ interrupts, however, can be cancelled by accessing the IRQ status register (ISR). Interrupts held pending due to edge detection are cleared by a power-on reset or a manual reset. Rev. 4.00 Dec 05, 2005 page 83 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) Program execution state Interrupt? Yes NMI? Yes No No User break? Yes No Level 15 interrupt? Yes Yes I3 to I0 level 14? No Yes No Level 14 interrupt? Yes I3 to I0 level 13? No Yes No Level 1 interrupt? Yes I3 to I0 = level 0? No No IRQOUT = low Save SR to stack Save PC to stack Copy accept-interrupt level to I3 to I0 IRQOUT = high Read exception vector table Branch to exception service routine *1 *2 Notes: I3 to I0 are Interrupt mask bits of status register (SR) in the CPU 1. IRQOUT is the same signal as interrupt request signal to the CPU (see figure 6.1). Therefore, IRQOUT is output when the request priority level is higher than the level in bits I3-I0 of SR. 2. When the accepted interrupt is sensed by edge, a high level is output from the IRQOUT pin at the moment when the CPU starts interrupt exception processing instead of instruction execution (namely, before saving SR to stack). However, if the interrupt controller accepts an interrupt with a higher priority than the interrupt just to be accepted and has output an interrupt request to the CPU, the IRQOUT pin holds low level. Figure 6.3 Interrupt Sequence Flowchart Rev. 4.00 Dec 05, 2005 page 84 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) 6.6.2 Stack after Interrupt Exception Processing Figure 6.4 shows the stack after interrupt exception processing. Address 4n-8 4n-4 4n PC*1 SR 32 bits 32 bits SP*2 Notes: 1. PC: Start address of the next instruction (return destination instruction) after the executing instruction 2. Always make sure that SP is a multiple of 4 Figure 6.4 Stack after Interrupt Exception Processing 6.7 Interrupt Response Time Table 6.3 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception processing starts and fetching of the first instruction of the interrupt service routine begins. Figure 6.5 shows an example of the pipeline operation when an IRQ interrupt is accepted. Rev. 4.00 Dec 05, 2005 page 85 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) Table 6.3 Interrupt Response Time Number of States Item DTC active judgment NMI, Peripheral Module 0 or 1 IRQ 1 Remarks 1 state required for interrupt signals for which DTC activation is possible Interrupt priority judgment and comparison with SR mask bits Wait for completion of sequence currently being executed by CPU 2 3 X ( 0) X ( 0) The longest sequence is for interrupt or addresserror exception processing (X = 4 + m1 + m2 + m3 + m4). If an interruptmasking instruction follows, however, the time may be even longer. Performs the saving PC and SR, and vector address fetch. Time from start of interrupt exception processing until fetch of first instruction of exception service routine starts Interrupt response time 5 + m1 + m2 + m3 5 + m1 + m2 + m3 Total: (7 or 8) + m1 + m2 + m3+X Minimum: 10 Maximum: 12 + 2 (m1 + m2 + m3) + m4 9 + m1 + m2 + m3 + X 12 13 + 2 (m1 + m2 + m3) + m4 0.25 0.3 s at 40 MHz 0.48 s at 40 MHz* Note: * 0.48 s at 40 MHz is the value in the case that m1 = m2 = m3 = m4 = 1. m1-m4 are the number of states needed for the following memory accesses. m1: SR save (longword write) m2: PC save (longword write) m3: Vector address read (longword read) m4: Fetch first instruction of interrupt service routine Rev. 4.00 Dec 05, 2005 page 86 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) Interrupt acceptance 5 + m1 + m2 + m3 1 IRQ Instruction (instruction replaced by interrupt exception processing) Overrun fetch Interrupt service routine start instruction F D E E MM E M E E 3 3 m1 m2 1 m3 1 F F D E F: Instruction fetch (instruction fetched from memory where program is stored). D: Instruction decoding (fetched instruction is decoded). E: Instruction execution (data operation and address calculation is performed according to the results of decoding). M: Memory access (data in memory is accessed). Figure 6.5 Example of the Pipeline Operation when an IRQ Interrupt is Accepted 6.8 Data Transfer with Interrupt Request Signals The following data transfers can be done using interrupt request signals: * Activate DTC only, CPU interrupts according to DTC settings The INTC masks CPU interrupts when the corresponding DTE bit is 1. The conditions for clearing DTE and interrupt source flag are listed below. DTE clear condition = DTC transfer end * DTECLR Interrupt source flag clear condition = DTC transfer end * DTECLR Where: DTECLR = DISEL + counter 0. Figure 6.6 shows a control block diagram. Rev. 4.00 Dec 05, 2005 page 87 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) Interrupt source CPU interrupt request DTC activation request DTER DTE clear DTECLR Transfer end Interrupt source flag clear (by DTC) Figure 6.6 Interrupt Control Block Diagram 6.8.1 Handling Interrupt Request Signals as Sources for DTC Activating and CPU Interrupt 1. For DTC, set the corresponding DTE bits and DISEL bits to 1. 2. Activating sources are applied to the DTC when interrupts occur. 3. When the DTC performs a data transfer, it clears the DTE bit to 0 and sends an interrupt request to the CPU. The activating source is not cleared. 4. The CPU clears interrupt sources in the interrupt processing routine then confirms the transfer counter value. When the transfer counter value is not 0, the CPU sets the DTE bit to 1 and allows the next data transfer. If the transfer counter value = 0, the CPU performs the necessary end processing in the interrupt processing routine. 6.8.2 Handling Interrupt Request Signals as Source for DTC Activating, but Not CPU Interrupt 1. For DTC, set the corresponding DTE bits to 1 and clear the DISEL bits to 0. 2. Activating sources are applied to the DTC when interrupts occur. 3. When the DTC performs a data transfer, it clears the activating source. An interrupt request is not sent to the CPU, because the DTE bit is hold to 1. 4. However, when the transfer counter value = 0 the DTE bit is cleared to 0 and an interrupt request is sent to the CPU. 5. The CPU performs the necessary end processing in the interrupt processing routine. Rev. 4.00 Dec 05, 2005 page 88 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) 6.8.3 Handling Interrupt Request Signals as Source for CPU Interrupt but Not DTC Activating 1. For DTC, clear the corresponding DTE bits to 0. 2. When interrupts occur, interrupt requests are sent to the CPU. 3. The CPU clears the interrupt source and performs the necessary processing in the interrupt processing routine. Rev. 4.00 Dec 05, 2005 page 89 of 564 REJ09B0270-0400 Section 6 Interrupt Controller (INTC) Rev. 4.00 Dec 05, 2005 page 90 of 564 REJ09B0270-0400 Section 7 User Break Controller (UBC) Section 7 User Break Controller (UBC) The user break controller (UBC) provides functions that make program debugging easier. By setting break conditions in the UBC, a user break interrupt is generated according to the contents of the bus cycle generated by the CPU or DTC. This function makes it easy to design an effective self-monitoring debugger, and customers of the chip can easily debug their programs without using a large in-circuit emulator. 7.1 Overview * There are 5 types of break compare conditions as follows: Address CPU cycle or DTC cycle Instruction fetch or data access Read or write Operand size: longword/word/byte * User break interrupt generated upon satisfying break conditions * User break interrupt generated before an instruction is executed by selecting break in the CPU instruction fetch. * Satisfaction of a break condition can be output to the UBCTRG pin. * Module standby mode can be set UBC0000A_000020010100 Rev. 4.00 Dec 05, 2005 page 91 of 564 REJ09B0270-0400 Section 7 User Break Controller (UBC) Figure 7.1 shows a block diagram of the UBC. Module bus Bus interface Internal bus UBCR UBBR UBAMRH UBAMRL UBARH UBARL Break condition comparator User break interrupt generating circuit Interrupt request Interrupt controller Trigger output generating circuit UBC UBARH, UBARL: UBAMRH, UBAMRL: UBBR: UBCR: User break address registers H, L User break address mask registers H, L User break bus cycle register User break control register UBCTRG pin output Figure 7.1 User Break Controller Block Diagram Rev. 4.00 Dec 05, 2005 page 92 of 564 REJ09B0270-0400 Section 7 User Break Controller (UBC) 7.2 Register Descriptions The UBC has the following registers. For details on register addresses and register states during each processing, refer to appendix A, Internal I/O Register. * User break address register H (UBARH) * User break address register L (UBARL) * User break address mask register H (UBAMRH) * User break address mask register L (UBAMRL) * User break bus cycle register (UBBR) * User break control register (UBCR) 7.2.1 User Break Address Register (UBAR) The user break address register (UBAR) consists of two registers: user break address register H (UBARH) and user break address register L (UBARL). Both are 16-bit readable/writable registers. UBARH specifies the upper bits (bits 31 to 16) of the address for the break condition, while UBARL specifies the lower bits (bits 15 to 0). The initial value of UBAR is H'00000000. * UBARH Bits 15 to 0: specifies user break address 31 to 16 (UBA31 to UBA16) * UBARL Bits 15 to 0: specifies user break address 15 to 0 (UBA15 to UBA0) 7.2.2 User Break Address Mask Register (UBAMR) The user break address mask register (UBAMR) consists of two registers: user break address mask register H (UBAMRH) and user break address mask register L (UBAMRL). Both are 16-bit readable/writable registers. UBAMRH specifies whether to mask any of the break address bits set in UBARH, and UBAMRL specifies whether to mask any of the break address bits set in UBARL. * UBAMRH Bits 15 to 0: specifies user break address mask 31 to 16 (UBM31 to UBM16) * UBAMRL Bits 15 to 0: specifies user break address mask 15 to 0 (UBM15 to UBM0) Rev. 4.00 Dec 05, 2005 page 93 of 564 REJ09B0270-0400 Section 7 User Break Controller (UBC) Initial Value All 0 Bit UBAMRH15 to UBAMRH 0 Bit Name UBM31 to UBM16 R/W R/W Description User Break Address Mask 31 to 16 0: Corresponding UBA bit is included in the break conditions 1: Corresponding UBA bit is not included in the break conditions UBAMRL15 to UBAMRL0 UBM15 to UBM0 All 0 R/W User Break Address Mask 15 to 0 0: Corresponding UBA bit is included in the break conditions 1: Corresponding UBA bit is not included in the break conditions 7.2.3 User Break Bus Cycle Register (UBBR) The user break bus cycle register (UBBR) is a 16-bit readable/writable register that sets the four break conditions. Bit 15 to 8 7 6 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. CP1 CP0 0 0 R/W R/W CPU Cycle/DTC Cycle Select 1 and 0 These bits specify break conditions for CPU cycles or DTC cycles. 00: No user break interrupt occurs 01: Break on CPU cycles 10: Break on DTC cycles 11: Break on both CPU and DTC cycles Rev. 4.00 Dec 05, 2005 page 94 of 564 REJ09B0270-0400 Section 7 User Break Controller (UBC) Initial Value 0 0 Bit 5 4 Bit Name ID1 ID0 R/W R/W R/W Description Instruction Fetch/Data Access Select1 and 0 These bits select whether to break on instruction fetch and/or data access cycles. 00: No user break interrupt occurs 01: Break on instruction fetch cycles 10: Break on data access cycles 11: Break on both instruction fetch and data access cycles 3 2 RW1 RW0 0 0 R/W R/W Read/Write Select 1 and 0 These bits select whether to break on read and/or write cycles 00: No user break interrupt occurs 01: Break on read cycles 10: Break on write cycles 11: Break on both read and write cycles Operand Size Select 1 and 0* These bits select operand size as a break condition. 00: Operand size is not a break condition 01: Break on byte access 10: Break on word access 11: Break on longword access 1 0 SZ1 SZ0 0 0 R/W R/W Note: * When breaking on an instruction fetch, clear the SZ0 bit to 0. All instructions are considered to be accessed in word-size (even when there are instructions in on-chip memory and two instruction fetches are performed simultaneously in one bus cycle). Operand size is word for instructions or determined by the operand size specified for the CPU/DTC data access. It is not determined by the bus width of the space being accessed. Rev. 4.00 Dec 05, 2005 page 95 of 564 REJ09B0270-0400 Section 7 User Break Controller (UBC) 7.2.4 User Break Control Register (UBCR) The user break control register (UBCR) is a 16-bit readable/writable register that (1) enables or disables user break interrupts and (2) sets the pulse width of the UBCTRG signal output in the event of a break condition match. Bit 15 to 3 2 1 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0 These bits specify the pulse width of the UBCTRG signal output in the event of a condition match. 00: UBCTRG pulse width is 01: UBCTRG pulse width is /4 10: UBCTRG pulse width is /8 11: UBCTRG pulse width is /16 Note: means internal clock 0 UBID 0 R/W User Break Disable Enables or disables user break interrupt request generation in the event of a user break condition match. 0: User break interrupt request is enabled 1: User break interrupt request is disabled Rev. 4.00 Dec 05, 2005 page 96 of 564 REJ09B0270-0400 Section 7 User Break Controller (UBC) 7.3 7.3.1 Operation Flow of the User Break Operation The flow from setting of break conditions to user break interrupt exception processing is described below: 1. The user break addresses are set in the user break address register (UBAR), the desired masked bits in the addresses are set in the user break address mask register (UBAMR) and the breaking bus cycle type is set in the user break bus cycle register (UBBR). If even one of the three groups of the UBBR's CPU cycle/DTC cycle select bits (CP1, CP0), instruction fetch/data access select bits (ID1, ID0), and read/write select bits (RW1, RW0) is set to 00 (no user break generated), no user break interrupt will be generated even if all other conditions are satisfied. When using user break interrupts, always be certain to establish bit conditions for all of these three groups. 2. The UBC uses the method shown in figure 7.2 to determine whether set conditions have been satisfied or not. When the set conditions are satisfied, the UBC sends a user break interrupt request signal to the interrupt controller (INTC). At the same time, a condition match signal is output at the UBCTRG pin with the pulse width set in bits CKS1 and CKS0. 3. The interrupt controller checks the accepted user break interrupt request signal's priority level. The user break interrupt has priority level 15, so it is accepted only if the interrupt mask level in bits I3-I0 in the status register (SR) is 14 or lower. When the I3-I0 bit level is 15, the user break interrupt cannot be accepted but it is held pending until user break interrupt exception processing can be carried out. Consequently, user break interrupts within NMI exception service routines cannot be accepted, since the I3-I0 bit level is 15. However, if the I3-I0 bit level is changed to 14 or lower at the start of the NMI exception service routine, user break interrupts become acceptable thereafter. See Section 6 Interrupt Controller (INTC) for the details on the handling of priority levels. 4. The INTC sends the user break interrupt request signal to the CPU, which begins user break interrupt exception processing upon receipt. See Section 6.6 Interrupt Operation, for the details on interrupt exception processing. Rev. 4.00 Dec 05, 2005 page 97 of 564 REJ09B0270-0400 Section 7 User Break Controller (UBC) UBARH/UBARL UBAMRH/UBAMRL 32 32 32 Internal address bits 31-0 32 32 CP1 CP0 CPU cycle DTC cycle ID1 ID0 Instruction fetch User break interrupt Data access RW1 Read cycle RW0 Write cycle SZ1 SZ0 Byte size Word size Longword size UBID Figure 7.2 Break Condition Determination Method Rev. 4.00 Dec 05, 2005 page 98 of 564 REJ09B0270-0400 Section 7 User Break Controller (UBC) 7.3.2 Break on On-Chip Memory Instruction Fetch Cycle Data in on-chip memory (on-chip ROM and/or RAM) is always accessed as 32-bits data in one bus cycle. Therefore, two instructions can be retrieved in one bus cycle when fetching instructions from on-chip memory. At such times, only one bus cycle is generated, but it is possible to cause independent breaks by setting the start addresses of both instructions in the user break address register (UBAR). In other words, when wanting to effect a break using the latter of two addresses retrieved in one bus cycle, set the start address of that instruction in UBAR. The break will occur after execution of the former instruction. 7.3.3 Program Counter (PC) Values Saved Break on Instruction Fetch: The program counter (PC) value saved to the stack in user break interrupt exception processing is the address that matches the break condition. The user break interrupt is generated before the fetched instruction is executed. If a break condition is set in an instruction fetch cycle placed immediately after a delayed branch instruction (delay slot), or on an instruction that follows an interrupt-disabled instruction, however, the user break interrupt is not accepted immediately, but the break condition establishing instruction is executed. The user break interrupt is accepted after execution of the instruction that has accepted the interrupt. In this case, the PC value saved is the start address of the instruction that will be executed after the instruction that has accepted the interrupt. Break on Data Access (CPU/DTC): The program counter (PC) value is the top address of the next instruction after the last instruction executed before the user break exception processing started. When data access (CPU/DTC) is set as a break condition, the place where the break will occur cannot be specified exactly. The break will occur at the instruction fetched close to where the data access that is to receive the break occurs. Rev. 4.00 Dec 05, 2005 page 99 of 564 REJ09B0270-0400 Section 7 User Break Controller (UBC) 7.4 Examples of Use Break on CPU Instruction Fetch Cycle 1. Register settings: UBARH = H'0000 UBARL = H'0404 UBBR = H'0054 UBCR = H'0000 Conditions set: Address: H'00000404 Bus cycle: CPU, instruction fetch, read (operand size is not included in conditions) Interrupt requests enabled A user break interrupt will occur before the instruction at address H'00000404. If it is possible for the instruction at H'00000402 to accept an interrupt, the user break exception processing will be executed after execution of that instruction. The instruction at H'00000404 is not executed. The PC value saved is H'00000404. 2. Register settings: UBARH = H'0015 UBARL = H'389C UBBR = H'0058 UBCR = H'0000 Conditions set: Address: H'0015389C Bus cycle: CPU, instruction fetch, write (operand size is not included in conditions) Interrupt requests enabled A user break interrupt does not occur because the instruction fetch cycle is not a write cycle. 3. Register settings: UBARH = H'0003 UBARL = H'0147 UBBR = H'0054 UBCR = H'0000 Conditions set: Address: H'00030147 Bus cycle: CPU, instruction fetch, read (operand size is not included in conditions) Interrupt requests enabled A user break interrupt does not occur because the instruction fetch was performed for an even address. However, if the first instruction fetch address after the branch is an odd address set by these conditions, user break interrupt exception processing will be carried out after address error exception processing. Rev. 4.00 Dec 05, 2005 page 100 of 564 REJ09B0270-0400 Section 7 User Break Controller (UBC) Break on CPU Data Access Cycle 1. Register settings: UBARH = H'0012 UBARL = H'3456 UBBR = H'006A UBCR = H'0000 Conditions set: Address: H'00123456 Bus cycle: CPU, data access, write, word Interrupt requests enabled A user break interrupt occurs when word data is written into address H'00123456. 2. Register settings: UBARH = H'00A8 UBARL = H'0391 UBBR = H'0066 UBCR = H'0000 Conditions set: Address: H'00A80391 Bus cycle: CPU, data access, read, word Interrupt requests enabled A user break interrupt does not occur because the word access was performed on an even address. Break on DTC Cycle 1. Register settings: UBARH = H'0076 UBARL = H'BCDC UBBR = H'00A7 UBCR = H'0000 Conditions set: Address: H'0076BCDC Bus cycle: DTC, data access, read, longword Interrupt requests enabled A user break interrupt occurs when longword data is read from address H'0076BCDC. 2. Register settings: UBARH = H'0023 UBARL = H'45C8 UBBR = H'0094 UBCR = H'0000 Conditions set: Address: H'002345C8 Bus cycle: DTC, instruction fetch, read (operand size is not included in conditions) Interrupt requests enabled Rev. 4.00 Dec 05, 2005 page 101 of 564 REJ09B0270-0400 Section 7 User Break Controller (UBC) A user break interrupt does not occur because no instruction fetch is performed in the DTC cycle. 7.5 7.5.1 Usage Notes Simultaneous Fetching of Two Instructions Two instructions may be simultaneously fetched in instruction fetch operation. Once a break condition is set on the latter of these two instructions, a user break interrupt will occur before the latter instruction, even though the contents of the UBC registers are modified to change the break conditions immediately after the fetching of the former instruction. 7.5.2 Instruction Fetches at Branches When a conditional branch instruction or TRAPA instruction causes a branch, the order of instruction fetching and execution is as follows: 1. When branching with a conditional branch instruction: BT and BF instructions When branching with a TRAPA instruction: a. Instruction fetch order Branch instruction fetch next instruction overrun fetch overrun fetch of instruction after the next branch destination instruction fetch b. Instruction execution order Branch instruction execution branch destination instruction execution 2. When branching with a delayed conditional branch instruction: BT/S and BF/S instructions a. Instruction fetch order Branch instruction fetch next instruction fetch (delay slot) overrun fetch of instruction after the next branch destination instruction fetch b. Instruction execution order Branch instruction execution delay slot instruction execution branch destination instruction execution Thus, when a conditional branch instruction or TRAPA instruction causes a branch, the branch destination instruction will be fetched after an overrun fetch of the next instruction or the instruction after the next. However, as the instruction that is the object of the break does not break until fetching and execution of the instruction have been confirmed, the overrun fetches described above do not become objects of a break. TRAPA instruction Rev. 4.00 Dec 05, 2005 page 102 of 564 REJ09B0270-0400 Section 7 User Break Controller (UBC) If data accesses are also included in break conditions besides instruction fetch, a break will occur because the instruction overrun fetch is also regarded as satisfying the data break condition. 7.5.3 Contention between User Break and Exception Processing If a user break is set for the fetch of a particular instruction, and exception processing with higher priority than a user break is in contention and is accepted in the decode stage for that instruction (or the next instruction), user break exception processing may not be performed after completion of the higher-priority exception service routine (on return by RTE). Thus, if a user break condition is specified to the branch destination instruction fetch after a branch (BRA, BRAF, BT, BF, BT/S, BF/S, BSR, BSRF, JMP, JSR, RTS, RTE, exception processing), and that branch instruction accepts an exception processing with higher priority than a user break interrupt, user break exception processing is not performed after completion of the exception service routine. Therefore, a user break condition should not be set for the fetch of the branch destination instruction after a branch. 7.5.4 Break at Non-Delay Branch Instruction Jump Destination When a branch instruction without delay slot (including exception processing) jumps to the destination instruction by executing the branch, a user break will not be generated even if a user break condition has been set for the first jump destination instruction fetch. 7.5.5 User Break Trigger Output Information on internal bus condition matches monitored by the UBC is output as UBCTRG. The trigger width can be set with clock select bits 1 and 0 (CKS1, CKS0) in the user break control register (UBCR). If a condition match occurs again during trigger output, the UBCTRG pin continues to output a low level, and outputs a pulse of the length set in bits CKS1 and CKS0 from the cycle in which the last condition match occurs. The trigger output conditions differ from those in the case of a user break interrupt when a CPU instruction fetch condition is satisfied. When a condition match occurs in an overrun fetch instruction as described in Section 7.5.2, Instruction Fetch at Branches, a user break interrupt is not requested but a trigger is output from the UBCTRG pin. Rev. 4.00 Dec 05, 2005 page 103 of 564 REJ09B0270-0400 Section 7 User Break Controller (UBC) In other CPU data accesses and DTC bus cycles, pulse is output under the conditions similar to user break interrupt conditions. Setting the user break interrupt disable (UBID) bit to 1 in UBCR enables trigger output to be monitored externally without requesting a user break interrupt. 7.5.6 Module Standby Mode Setting The UBC can set the module disable/enable by using the module standby control register 2 (MSTCR2). By releasing the module standby mode, register access becomes to be enabled. By setting the MSTP0 bit of MSTCR2 to 1, the UBC is in the module standby mode in which the clock supply is halted. See section 21, Power-Down Modes, for further details. Rev. 4.00 Dec 05, 2005 page 104 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) Section 8 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. Figure 8.1 shows a block diagram of the DTC. The DTC's register information is stored in the on-chip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. 8.1 Features * Transfer possible over any number of channels * Three transfer modes Normal, repeat, and block transfer modes available * One activation source can trigger a number of data transfers (chain transfer) * Direct specification of 32-bit address space possible * Activation by software is possible * Transfer can be set in byte, word, or longword units * The interrupt that activated the DTC can be requested to the CPU * Module standby mode can be set DTCSH20B_000020020700 Rev. 4.00 Dec 05, 2005 page 105 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) On-chip ROM On-chip RAM Register control DTMR DTCR DTSAR Activation control DTDAR DTIAR CPU interrupt request source clear control Interrupt request Request priority control DTER DTCSR DTBR Bus interface DTC module bus DTC Bus controller Legend: DTMR: DTCR: DTSAR: DTDAR: DTC mode register DTC transfer count register DTC source address register DTC destination address register Internal bus On-chip peripheral module Peripheral bus DTIAR: DTER: DTCSR: DTBR: DTC initial address register DTC enable register DTC control/status register DTC information base register Figure 8.1 Block Diagram of DTC Rev. 4.00 Dec 05, 2005 page 106 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) 8.2 Register Descriptions DTC has the following registers. * DTC mode register (DTMR) * DTC source address register (DTSAR) * DTC destination address register (DTDAR) * DTC initial address register (DTIAR) * DTC transfer count register A (DTCRA) * DTC transfer count register B (DTCRB) These six registers cannot be directly accessed from the CPU. When activated, the DTC transfer desired set of register information that is stored in an on-chip RAM to the corresponding DTC registers. After the data transfer, it writes a set of updated register information back to the RAM. * DTC enable register A (DTEA) * DTC enable register B (DTEB) * DTC enable register C (DTEC) * DTC enable register D (DTED) * DTC enable register E (DTEE) * DTC enable register F (DTEF) * DTC control/status register (DTCSR) * DTC information base register (DTBR) For details on register addresses and register states during each processing, refer to appendix A, Internal I/O Register. Rev. 4.00 Dec 05, 2005 page 107 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) 8.2.1 DTC Mode Register (DTMR) DTMR is a 16-bit register that selects the DTC operating mode. Bit 15 14 Bit Name SM1 SM0 Initial Value Undefined Undefined R/W Description Source Address Mode 1 and 0 These bits specify a DTSAR operation after a data transfer. 0x: DTSAR is fixed 10: DTSAR is incremented after a transfer (by +1 when Sz 1 and 0 = 00; by +2 when Sz 1 and 0 = 01; by +4 when Sz 1 and 0 = 10) 11: DTSAR is decremented after a transfer (by -1 when Sz 1 and 0 = 00; by -2 when Sz 1 and 0 = 01; by -4 when Sz 1 and 0 = 10) 13 12 DM1 DM0 Undefined Undefined Destination Address Mode 1 and 0 These bits specify a DTDAR operation after a data transfer. 0x: DTDAR is fixed 10: DTDAR is incremented after a transfer (by +1 when Sz 1 and 0 = 00; by +2 when Sz 1 and 0 = 01; by +4 when Sz 1 and 0 = 10) 11: DTDAR is decremented after a transfer (by -1 when Sz 1 and 0 = 00; by -2 when Sz 1 and 0 = 01; by -4 when Sz 1 and 0 = 10) 11 10 MD1 MD0 Undefined Undefined DTC Mode 1 and 0 These bits specify the DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited 9 8 Sz1 Sz0 Undefined Undefined DTC Data Transfer Size 1 and 0 Specify the size of data to be transferred. 00: Byte-size transfer 01: Word-size transfer 10: longword-size transfer 11: Setting prohibited Rev. 4.00 Dec 05, 2005 page 108 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) Initial Value Undefined Bit 7 Bit Name DTS R/W Description DTC Transfer Mode Select Specifies whether the source or the destination is set to be a repeat area or block area, in repeat mode or block transfer mode. 0: Destination is repeat area or block area 1: Source is repeat area or block area 6 CHNE Undefined DTC Chain Transfer Enable When this bit is set to 1, a chain transfer will be performed. 0: Chain transfer is canceled 1: Chain transfer is set In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the activation source flag, and clearing of DTER is not performed. 5 DISEL Undefined DTC Interrupt Select When this bit is set to 1, a CPU interrupt request is generated for every DTC transfer. When this bit is set to 0, a CPU interrupt request is generated at the time when the specified number of data transfer ends. 4 NMIM Undefined DTC NMI Mode This bit designates whether to terminate transfers when an NMI is input during DTC transfers. 0: Terminate DTC transfer upon an NMI 1: Continue DTC transfer until end of transfer being executed 3 to 0 All Undefined Reserved These bits have no effect on DTC operation and should always be written with 0. X: Don't care Rev. 4.00 Dec 05, 2005 page 109 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) 8.2.2 DTC Source Address Register (DTSAR) The DTC source address register (DTSAR) is a 32-bit register that specifies the DTC transfer source address. Specify an even address in case the transfer size is word; specify a multiple-offour address in case of longword. The initial value is undefined. 8.2.3 DTC Destination Address Register (DTDAR) The DTC destination address register (DTDAR) is a 32-bit register that specifies the DTC transfer destination address. Specify an even address in case the transfer size is word; specify a multipleof-four address in case of longword. The initial value is undefined. 8.2.4 DTC Initial Address Register (DTIAR) The DTC initial address register (DTIAR) is a 32-bit register that specifies the initial transfer source/transfer destination address in repeat mode. In repeat mode, when the DTS bit is set to 1, specify the initial transfer source address in the repeat area, and when the DTS bit is cleared to 0, specify the initial transfer destination address in the repeat area. The initial value is undefined. 8.2.5 DTC Transfer Count Register A (DTCRA) DTCRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. The initial value is undefined. In normal mode, the entire DTCRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. The number of transfers is 1 when the set value is H'0001, 65535 when it is H'FFFF, and 65536 when it is H'0000. In repeat mode, DTCRAH maintains the transfer count and DTCRAL functions as an 8-bit transfer counter. The number of transfers is 1 when the set value is DTCRAH = DTCRAL = H'01, 255 when they are H'FF, and 256 when it is H'00. In block transfer mode, it functions as a 16-bit transfer counter. The number of transfers is 1 when the set value is H'0001, 65535 when it is H'FFFF, and 65536 when it is H'0000. 8.2.6 DTC Transfer Count Register B (DTCRB) The DTCRB is a 16-bit register that designates the block length in block transfer mode. The block length is 1 when the set value is H'0001, 65535 when it is H'FFFF, and 65536 when it is H'0000. The initial value is undefined. Rev. 4.00 Dec 05, 2005 page 110 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) 8.2.7 DTC Enable Registers (DTER) DTER which is comprised of seven registers, DTEA to DTEF, is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTE bits is shown in table 8.1. Bit 7 6 5 4 3 2 1 0 Bit Name DTE*7 DTE*6 DTE*5 DTE*4 DTE*3 DTE*2 DTE*1 DTE*0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description DTC Activation Enable 7 to 0 Setting this bit to 1 specifies the corresponding interrupt source to a DTC activation source. [Clearing conditions] * * * When the DISEL bit is 1 and the data transfer has ended When the specified number of transfers have ended 0 is written to the bit to be cleared after 1 has been read from the bit These bits are not cleared when the DISEL bit is 0 and the specified number of transfers have not ended. [Setting condition] 1 is written to the bit to be set after a 0 has been read from the bit Note: * The last character of the DTC enable register's name comes here. Example: DTEB3 in DTEB, etc. Rev. 4.00 Dec 05, 2005 page 111 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) 8.2.8 DTC Control/Status Register (DTCSR) The DTCSR is a 16-bit readable/writable register that disables/enables DTC activation by software and sets the DTC vector addresses for software activation. It also indicates the DTC transfer status. Bit 15 14 13 12 11 10 Bit Name NMIF Initial Value 0 0 0 0 0 0 R/W R R R R R 1 R/(W)* Description Reserved These bits have no effect on DTC operation and should always be written with 0. NMI Flag Bit This bit indicates that an NMI interrupt has occurred. 0: No NMI interrupts [Clearing condition] * Write 0 after reading the NMIF bit 1: NMI interrupt has been generated When the NMIF bit is set, DTC transfers are not allowed even if the DTER bit is set to 1. If, however, a transfer has already started with the NMIM bit of the DTMR set to 1, execution will continue until that transfer ends. 9 AE 0 R/(W)* 1 Address Error Flag This bit indicates that an address error by the DTC has occurred. 0: No address error by the DTC [Clearing condition] * Write 0 after reading the AE bit 1: An address error by the DTC occurred When the AE bit is set, DTC transfers are not allowed even if the DTER bit is set to 1. 8 SWDTE 0 R/W* 2 DTC Software Activation Enable Setting this bit to 1 activates DTC. 0: DTC activation by software disabled 1: DTC activation by software enabled Rev. 4.00 Dec 05, 2005 page 112 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 Bit Name DTVEC7 DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description DTC Software Activation Vectors 7 to 0 These bits specify the lower eight bits of the vector addresses for DTC activation by software. A vector address is calculated as H'0400 + DTVEC (7:0). Always specify 0 for DTVEC0. For example, when DTVEC7 to DTVEC0 = H'10, the vector address is H'0410. When the bit SWDTE is 0, these bits can be written to. Notes: 1. For the NMIF and AE bits, only a 0 write after a 1 read is possible. 2. For the SWDTE bit, a 1 write is always possible, but a 0 write is possible only after a 1 is read. 8.2.9 DTC Information Base Register (DTBR) The DTBR is a 16-bit readable/writable register that specifies the upper 16 bits of the memory address containing DTC transfer information. Always access the DTBR in word or longword units. If it is accessed in byte units the register contents will become undefined at the time of a write, and undefined values will be read out upon reads. The initial value is undefined. 8.3 8.3.1 Operation Activation Sources The DTC operates when activated by an interrupt or by a write to DTCSR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTER bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or corresponding DTER bit is cleared. The activation source flag, in the case of RXI_2, for example, is the RDRF flag of SCI2. When a DTC is activated by an interrupt, existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities. Figure 8.2 shows a block diagram of activation source control. For details see section 6, Interrupt Controller (INTC). Rev. 4.00 Dec 05, 2005 page 113 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) CPU interrupt requests (those not designated as DTC activating sources) Interrupt requests IRQ on-chip peripheral Source flag clear DTC DTER Clear DTC activation request INTC DTC control Figure 8.2 Activating Source Control Block Diagram 8.3.2 Location of Register Information and DTC Vector Table Figure 8.3 shows the allocation of register information in memory space. The register information start addresses are designated by DTBR for the upper 16 bits, and the DTC vector table for the lower 16 bits. The allocation in order from the register information start address in normal mode is DTMR, DTCRA, 4 bytes empty (no effect on DTC operation), DTSAR, then DTDAR. In repeat mode it is DTMR, DTCRA, DTIAR, DTSAR, and DTDAR. In block transfer mode, it is DTMR, DTCRA, 2 bytes empty (no effect on DTC operation), DTCRB, DTSAR, then DTDAR. Fundamentally, certain RAM areas are designated for addresses storing register information. Memory space Register information start address Memory space Memory space DTMR DTCRA DTMR DTCRA DTIAR DTMR DTCRA DTCRB DTSAR DTDAR Register information DTSAR DTDAR DTSAR DTDAR Normal mode Repeat mode Block transfer mode Figure 8.3 DTC Register Information Allocation in Memory Space Rev. 4.00 Dec 05, 2005 page 114 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) Figure 8.4 shows the correspondence between DTC vector addresses and register information allocation. For each DTC activating source there are 2 bytes in the DTC vector table, which contain the register information start address. Table 8.1 shows the correspondence between activating sources and vector addresses. When activating with software, the vector address is calculated as H'0400 + DTVEC[7:0]. Through DTC activation, a register information start address is read from the vector table, then register information placed in memory space is read from that register information start address. Always designate register information start addresses in multiples of four. DTBR Transfer information start address (upper 16 bits) DTC vector table Register information DTC vector address Register information start address (lower 16 bits) Memory space Figure 8.4 Correspondence between DTC Vector Address and Transfer Information Rev. 4.00 Dec 05, 2005 page 115 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) Table 8.1 Activating Source Generator MTU (CH4) Interrupt Sources, DTC Vector Addresses, and Corresponding DTEs Activating Source TGI4A TGI4B TGI4C TGI4D TGI4V DTC Vector Address H'00000400 H'00000402 H'00000404 H'00000406 H'00000408 H'0000040A H'0000040C H'0000040E H'00000410 H'00000412 H'00000414 H'00000416 H'00000418 H'0000041A H'0000041C H'0000041E H'00000420 H'00000422 H'00000424 H'00000426 H'00000428 H'0000042A H'0000042C H'0000042E H'00000430 H'00000432 Transfer Source Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* ADDR Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Transfer Destination Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* Low DTE Bit DTEA7 DTEA6 DTEA5 DTEA4 DTEA3 DTEA2 DTEA1 DTEA0 DTEB7 DTEB6 DTEB5 DTEB4 DTEB3 DTEB2 DTEB1 DTEB0 DTEC7 DTEC6 DTEC5 DTEC4 DTEC3 DTEC2 DTEC1 DTEC0 DTED7 DTED6 Priority High MTU (CH3) TGI3A TGI3B TGI3C TGI3D MTU (CH2) MTU (CH1) MTU (CH0) TGI2A TGI2B TGI1A TGI1B TGI0A TGI0B TGI0C TGI0D A/D converter (CH0) External pin ADI0 IRQ0 IRQ1 IRQ2 IRQ3 (Reserved by system) (Reserved by system) (Reserved by system) (Reserved by system) Rev. 4.00 Dec 05, 2005 page 116 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) Activating Source Generator CMT (CH0) CMT (CH1) Reserved A/D converter (CH1) A/D converter (CH2) SCI2 SCI3 Reserved MMT Reserved Software Note: * Activating Source CMI0 CMI1 ADI1 ADI2 RXI_2 TXI_2 RXI_3 TXI_3 TGN TGM Write to DTCSR DTC Vector Address H'00000434 H'00000436 H'00000438- 00000443 H'00000444 H'00000446 H'00000448 H'0000044A H'0000044C H'0000044E H'00000450- H'00000453 H'00000454 H'00000456 H'00000458- H'0000049F H'0400+ DTVEC[7:0] DTE Bit DTED5 DTED4 DTEE5 DTEE4 DTEE3 DTEE2 DTEE1 DTEE0 DTEF5 DTEF4 Transfer Source Arbitrary* Arbitrary* ADDR ADDR RDR_2 Arbitrary* RDR_3 Arbitrary* Arbitrary* Arbitrary* Arbitrary* Transfer Destination Arbitrary* Arbitrary* Arbitrary* Arbitrary* Arbitrary* TDR_2 Arbitrary* TDR_3 Arbitrary* Arbitrary* Arbitrary* Priority High Low On-chip memory, on-chip peripheral modules (excluding DTC) 8.3.3 DTC Operation Register information is stored in an on-chip RAM. When activated, the DTC reads register information in an on-chip RAM and transfers data. After the data transfer, it writes updated register information back to the RAM. Pre-storage of register information in the RAM makes it possible to transfer data over any required number of channels. The transfer mode can be specified as normal, repeat, and block transfer mode. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single activation source (chain transfer). The 32-bit DTSAR designates the DTC transfer source address and the 32-bit DTDAR designates the transfer destination address. After each transfer, DTSAR and DTDAR are independently incremented, decremented, or left fixed depending on its register information. Rev. 4.00 Dec 05, 2005 page 117 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) Start Initial settings DTMR, DTCR, DTIAR, DTSAR, DTDAR NMIF = AE = 0? Yes Transfer request generated? Yes DTC vector read No No Transfer information read DTCRA = DTCRA - 1 (normal/block transfer mode) DTCRAL = DTCRAL - 1 (repeat mode) Transfer (1 transfer unit) DTSAR, DTDAR update DTCRB = DTCRB - 1 (block transfer mode) Block transfer mode and DTCRB 0? No Transfer information write NMIF * NMIM + AE = 1? Yes Transfer information write No Yes NMI or address error CHNE = 0? Yes No CPU interrupt request When DISEL = 1 or DTCRA = 0 (normal/block transfer mode) When DISEL = 1 (repeat transfer mode) End Figure 8.5 DTC Operation Flowchart Rev. 4.00 Dec 05, 2005 page 118 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) Normal Mode: Performs the transfer of one byte, one word, or one longword for each activation. The total transfer count is 1 to 65536. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 8.2 Normal Mode Register Functions Values Written Back upon a Transfer Information Write Register DTMR DTCRA DTSAR DTDAR Function Operation mode control Transfer count Transfer source address Transfer destination address When DTCRA is other than 1 DTMR DTCRA - 1 Increment/decrement/fixed Increment/decrement/fixed When DTCRA is 1 DTMR DTCRA - 1 (= H'0000) Increment/decrement/fixed Increment/decrement/fixed DTSAR Transfer DTDAR Figure 8.6 Memory Mapping in Normal Mode Repeat Mode: Performs the transfer of one byte, one word, or one longword for each activation. Either the transfer source or transfer destination is designated as the repeat area. Table 8.3 lists the register information in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Rev. 4.00 Dec 05, 2005 page 119 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) Table 8.3 Repeat Mode Register Functions Values Written Back upon a Transfer Information Write Register DTMR DTCRAH DTCRAL DTIAR DTSAR Function Operation mode control Transfer count save Transfer count Initial address Transfer source address Transfer destination address When DTCRA is other than 1 DTMR DTCRAH DTCRAL - 1 (Not written back) Increment/decrement/fixed When DTCRA is 1 DTMR DTCRAH DTCRAH (Not written back) (DTS = 0) Increment/ decrement/fixed (DTS = 1) DTIAR (DTS = 0) DTIAR (DTS = 1) Increment/ decrement/fixed DTDAR Increment/decrement/fixed DTSAR or DTDAR Repeat area Transfer DTDAR or DTSAR Figure 8.7 Memory Mapping in Repeat Mode Block Transfer Mode: Performs the transfer of one block for each one activation. Either the transfer source or transfer destination is designated as the block area. The block length is specified between 1 and 65536. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. Rev. 4.00 Dec 05, 2005 page 120 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt is requested. Table 8.4 Register DTMR DTCRA DTCRB DTSAR DTDAR Block Transfer Mode Register Functions Function Operation mode control Transfer count Block length Transfer source address Transfer destination address Values Written Back upon a Transfer Information Write DTMR DTCRA - 1 (Not written back) (DTS = 0) Increment/ decrement/ fixed (DTS = 1) DTSAR initial value (DTS = 0) DTDAR initial value (DTS = 1) Increment/ decrement/ fixed First block DTSAR or DTDAR * * * Block area Transfer DTDAR or DTSAR Nth block Figure 8.8 Memory Mapping in Block Transfer Mode Rev. 4.00 Dec 05, 2005 page 121 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) Chain Transfer: Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in a single activation source. DTSAR, DTDAR, DTMR, DTCRA, and DTCRB can be set independently. Figure 8.9 shows the chain transfer. When activated, the DTC reads the register information start address stored at the vector address, and then reads the first register information at that start address. After the data transfer, the CHNE bit will be tested. When it has been set to 1, DTC reads next register information located in a consecutive area and performs the data transfer. These sequences are repeated until the CHNE bit is cleared to 0. In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. Source Register information CHNE = 1 DTC vector address Register information start address Register information CHNE = 0 Destination Source Destination Figure 8.9 Chain Transfer Rev. 4.00 Dec 05, 2005 page 122 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) 8.3.4 Interrupt Source An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control. In the case of activation by software, a software activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine should clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. Note: When the DTCR contains a value equal to or greater than 2, the SWDTE bit is automatically cleared to 0. When the DTCR is set to 1, the SWDTE bit is again set to 1. 8.3.5 Operation Timing When register information is located in on-chip RAM, each mode requires 4 cycles for transfer information reads, and 3 cycles for writes. Activating source DTC request Address Vector read Transfer information read R W Data transfer Transfer information write Figure 8.10 DTC Operation Timing Example (Normal Mode) Rev. 4.00 Dec 05, 2005 page 123 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) 8.3.6 DTC Execution State Counts Table 8.5 shows the execution state for one DTC data transfer. Furthermore, Table 8.6 shows the state counts needed for execution state. Table 8.5 Execution State of DTC Register Information Read/Write J 7 7 7 Internal Operation M 1 1 1 Mode Normal Repeat Block transfer Vector Read I 1 1 1 Data Read K 1 1 N Data Write L 1 1 N Note: N means a block size (default set values of DTCRB) Table 8.6 State Counts Needed for Execution State On-chip RAM 32 1 SI SJ SK SK SK SL SL SL SM 1 1 1 1 1 1 1 1 On-chip ROM 32 1 1 1 1 1 1 1 1 1 1 Internal I/O Register 32 1 2* 2 2 4 2 2 4 1 32 2 3* 3 3 6 3 3 6 1 Access Objective Bus width Access state Execution state Vector read Register information read/write Byte data read Word data read Longword data read Byte data write Word data write Longword data write Internal operation Notes: 1. Two state access modules: Port, INT, CMT, SCI, etc. 2. Three state access modules: WDT, UBC, etc. The execution state count is calculated using the following formula. indicates the number of transfers by one activating source (count + 1 when CHNE bit is set to 1). Execution state count = I * SI + (J * SJ + K * SK + L * SL) + M * SM Rev. 4.00 Dec 05, 2005 page 124 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) 8.4 8.4.1 Procedures for Using DTC Activation by Interrupt The procedure for using the DTC with interrupt activation is as follows: 1. Set the DTMR, DTCRA, DTSAR, DTDAR, DTCRB, and DTIAR register information in memory space. 2. Establish the register information start address with DTBR and the DTC vector table. 3. Set the corresponding DTER bit to 1. 4. The DTC is activated when an interrupt source occurs. 5. When interrupt requests are not made to the CPU, the interrupt source is cleared, but the DTER is not. When interrupts are requested, the interrupt source is not cleared, but the DTER is. 6. Interrupt sources are cleared within the CPU interrupt routine. When doing continuous DTC data transfers, set the DTER to 1. 8.4.2 Activation by Software The procedure for using the DTC with software activation is as follows: 1. Set the DTMR, DTCRA, DTSAR, DTDAR, DTCRB, and DTIAR register information in memory space. 2. Set the start address of the register information in the DTC vector address. 3. Check that the SWDTE bit is 0. 4. Write 1 to SWDTE bit and the vector number to DTVEC. 5. Check the vector number written to DTVEC. 6. After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the SWDTE bit is held at 1 and a CPU interrupt is requested. 7. The SWDTE bit is cleared to 0 within the CPU interrupt routine. For continuous DTC data transfer, set the SWDTE bit to 1 after confirming that its current value is 0. Then write the vector number to DTVEC for continuous DTC transfer. Rev. 4.00 Dec 05, 2005 page 125 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) 8.4.3 DTC Use Example The following is a DTC use example of a 128-byte data reception by the SCI: 1. The settings are: DTMR source address fixed (SM1 = SM0 = 0), destination address incremented (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), byte size (SZ1 = SZ0 = 0), one transfer per activating source (CHNE = 0), and a CPU interrupt request after the designated number of data transfers (DISEL = 0). DTS bit can be set to any value. 128 (H'0080) is set in DTCRA, the RDR address of the SCI is set in DTSAR, and the start address of the RAM storing the receive data is set in DTDAR. DTCRB can be set to any value. 2. Set the register information start address with DTBR and the DTC vector table. 3. Set the corresponding DTER bit to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DTDAR is incremented and DTCRA is decremented. The RDRF flag is automatically cleared to 0. 6. When DTCRA is 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTER bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine should perform completion processing. Rev. 4.00 Dec 05, 2005 page 126 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) 8.5 8.5.1 Cautions on Use Prohibition against DTC Register Access by DTC DTC register access by the DTC is prohibited. 8.5.2 Module Standby Mode Setting DTC operation can be disabled or enabled using the module standby control register. The initial setting is for DTC operation to be halted. Register access is enabled by clearing module standby mode. When the MSTP24 and MSTP25 bits in MSTCR1 are set to 1, the DTC clock is halted and the DTC enters module standby mode. Do not write 1 on MSTP24 bit or MSTP25 bit during activation of the DTC. For details, refer to section 21, Power-Down Modes. 8.5.3 On-Chip RAM The DTMR, DTSAR, DTDAR, DTCRA,DTCRB and DTIAR registers are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0. Rev. 4.00 Dec 05, 2005 page 127 of 564 REJ09B0270-0400 Section 8 Data Transfer Controller (DTC) Rev. 4.00 Dec 05, 2005 page 128 of 564 REJ09B0270-0400 Section 9 Bus State Controller (BSC) Section 9 Bus State Controller (BSC) The bus state controller (BSC) provides an access control function to the on-chip ROM, RAM and peripheral module register. 9.1 Features The BSC has the following features: * Bus arbitration between CPU and DTC * On-chip ROM and RAM interfaces On-chip ROM and RAM access of 32 bits in 1 state * On-chip module I/O register access control 9.2 Input/Output Pin This LSI has no input/output pin for the BSC module. 9.3 Register Configuration The BSC has four registers. For details on these register addresses and register states in each processing states, refer to appendix A, Internal I/O Register. * Bus control register 1 (BCR1) * RAM emulation register (RAMER) BSC1000B_000020020700 Rev. 4.00 Dec 05, 2005 page 129 of 564 REJ09B0270-0400 Section 9 Bus State Controller (BSC) Table 9.1 Address Map Size Bus Width 32 bits 32 bits 32 bits Address H'0000 0000 to H'0000 FFFF H'0001 0000 to H'0001 FFFF H'0002 0000 to H'0003 FFFF H'0004 0000 to H'001F FFFF H'0020 0000 to H'0023 FFFF H'0024 0000 to H'FFFF 7FFF Space* Memory SH7046F 64 kbytes 64 kbytes 128 kbytes SH7148 64 kbytes Reserved Reserved Reserved SH7048 64 kbytes 64 kbytes Reserved Reserved On-chip ROM On-chip ROM Reserved Reserved Reserved Reserved Reserved Reserved On-chip peripheral module Reserved Reserved H'FFFF 8000 to H'FFFF BFFF On-chip peripheral module H'FFFF C000 to H'FFFF CFFF Reserved 16 kbytes 16 kbytes 16kbytes 8, 16 bits Reserved 4 kbytes 4 kbytes 4 kbytes Reserved Reserved Reserved 4 kbytes Reserved Reserved Reserved 4 kbytes 32 bits 32 bits 32 bits H'FFFF D000 to H'FFFF DFFF On-chip RAM On-chip RAM H'FFFF E000 to H'FFFF EFFF H'FFFF F000 to H'FFFF FFFF Note: * Do not access reserved spaces. Operation cannot be guaranteed if they are accessed. Rev. 4.00 Dec 05, 2005 page 130 of 564 REJ09B0270-0400 Section 9 Bus State Controller (BSC) 9.4 9.4.1 Register Descriptions Bus Control Register 1 (BCR1) BCR1 is a 16-bit readable/writable register that enables access to the MMT and MTU control registers. Bit 15 Bit Name Initial Value 0 R/W R Description Reserved This bit is always read as 0 and should always be written with 0. 14 MMTRWE 1 R/W MMT Read/Write Enable This bit enables MMT control register access. For details, refer to MMT section. 0: MMT control register access is disabled 1: MMT control register access is enabled 13 MTURWE 1 R/W MTU Read/Write Enable This bit enables MTU control register access. For details, refer to MTU section. 0: MTU control register access is disabled 1: MTU control register access is enabled 12 to 8 All 0 R Reserved These bits are always read as 0 and should always be written with 0. 7 to 4 All 0 R Reserved These bits are always read as 0 and should always be written with 0. 3 to 0 All 1 R Reserved These bits are always read as 1 and should always be written with 1. 9.4.2 RAM Emulation Register (RAMER) The RAM emulation register (RAMER) is a 16-bit readable/writable register that selects the RAM area to be used when emulating realtime programming of flash memory. For details, refer to section 18.5.5, RAM Emulation Register. Rev. 4.00 Dec 05, 2005 page 131 of 564 REJ09B0270-0400 Section 9 Bus State Controller (BSC) 9.5 Bus Arbitration This LSI has a bus arbitration function that, when a bus release request is received from a bus masters, releases the bus to that module. There are two internal bus masters, the CPU and DTC. The priority for arbitrate the bus mastership between these bus masters is: DTC > CPU 9.6 On-chip Peripheral I/O Register Access On-chip peripheral I/O registers are accessed from the bus state controller, as shown in Table 9.2. Table 9.2 On-chip Peripheral Module Connected bus width Access cycle On-chip Peripheral I/O Register Access MTU, POE 16bit 1 SCI 8bit 2cyc* INTC 16bit 1 PFC, PORT CMT 16bit 2 A/D 16bit 1 UBC 16bit 1 WDT 16bit 2 DTC 16bit 2 MMT 16bit 2 16bit 1 2cyc* 2cyc* 2cyc* 2cyc* 2cyc* 3cyc* 3cyc* 3cyc* 2cyc* 1 Notes: 1. Converted to the peripheral clock. 2. Converted to the system clock. Rev. 4.00 Dec 05, 2005 page 132 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Section 10 Multi-Function Timer Pulse Unit (MTU) This LSI has an on-chip multi-function timer pulse unit (MTU) that comprises five 16-bit timer channels. The block diagram is shown in figure 10.1. 10.1 Features * Maximum 16-pulse input/output * Selection of 8 counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match Input capture function Counter clear operation Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture is possible Register simultaneous input/output is possible by synchronous counter operation A maximum 12-phase PWM output is possible in combination with synchronous operation * Buffer operation settable for channels 0, 3, and 4 * Phase counting mode settable independently for each of channels 1 and 2 * Cascade connection operation * Fast access via internal 16-bit bus * 23 interrupt sources * Automatic transfer of register data * A/D converter conversion start trigger can be generated * Module standby mode can be set * Positive and negative 3-phase waveforms (6-phase waveforms in total) can be output by channel 3 and channel 4 connected in complementary PWM or reset PWM mode * AC synchronous motor (brushless DC motor) drive mode can be set by channel 0, channel 3, and channel 4 connected in complementary PWM or reset PWM mode. * Selection of chopping or level waveform outputs in AC synchronous motor drive mode TIMMTU0A_020020020700 Rev. 4.00 Dec 05, 2005 page 133 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.1 MTU Functions Item Count clock Channel 0 P/1 P/4 P/16 P/64 TCLKA TCLKB TCLKC TCLKD TGRA_0 TGRB_0 TGRC_0 TGRD_0 TIOC0A TIOC0B TIOC0C TIOC0D TGR compare match or input capture Channel 1 P/1 P/4 P/16 P/64 P/256 TCLKA TCLKB TGRA_1 TGRB_1 TIOC1A TIOC1B Channel 2 P/1 P/4 P/16 P/64 P/1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 TIOC2A TIOC2B Channel 3 P/1 P/4 P/16 P/64 P/256 P/1024 TCLKA TCLKB TGRA_3 TGRB_3 TGRC_3 TGRD_3 TIOC3A TIOC3B TIOC3C TIOC3D TGR compare match or input capture Channel 4 P/1 P/4 P/16 P/64 P/256 P/1024 TCLKA TCLKB TGRA_4 TGRB_4 TGRC_4 TGRD_4 TIOC4A TIOC4B TIOC4C TIOC4D TGR compare match or input capture General registers General registers/ buffer registers I/O pins Counter clear function TGR compare match or input capture TGR compare match or input capture Compare match output 0 output 1 output Toggle output Input capture function Synchronous operation PWM mode 1 PWM mode 2 Complementary PWM mode Reset synchronous PWM mode AC synchronous motor drive mode Rev. 4.00 Dec 05, 2005 page 134 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Item Phase counting mode Buffer operation DTC activation TGR compare match or input capture Channel 0 TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture and TCNT overflow underflow TGRA_4 compare match or input capture 5 sources * Compare match or input capture 4A * Compare match or input capture 4B * Compare match or input capture 4C * Compare match or input capture 4D * Overflow/ Underflow Channel 1 Channel 2 Channel 3 Channel 4 A/D converter start trigger TGRA_0 compare match or input capture 5 sources * Compare match or input capture 0A * Compare match or input capture 0B * Compare match or input capture 0C * Compare match or input capture 0D * Overflow TGRA_1 compare match or input capture 4 sources * Compare match or input capture 1A * Compare match or input capture 1B * Overflow * Underflow TGRA_2 compare match or input capture 4 sources * Compare match or input capture 2A * Compare match or input capture 2B * Overflow * Underflow TGRA_3 compare match or input capture 5 sources * Compare match or input capture 3A * Compare match or input capture 3B * Compare match or input capture 3C * Compare match or input capture 3D * Overflow Interrupt sources Notes: : Possible : Not possible Rev. 4.00 Dec 05, 2005 page 135 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) TIORL TMDR Channel 3 TSR TGRC TGRD TGRA TGRB TCNT Input/output pins Channel 3: TIOC3A TIOC3B TIOC3C TIOC3D Channel 4: TIOC4A TIOC4B TIOC4C TIOC4D Control logic for channels 3 and 4 Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TCI4C TCI4D TGI4V TIORH TIORL TMDR Channel 4 TSR TIER TCR TGRC TDDR TIORH TOCR TGCR TIER TCR TCNTS TCDR TMDR Channel 2 TSR Clock input Internal clock: /1 /4 /16 /64 /256 /1024 External clock: TCLKA TCLKB TCLKC TCLKD TOER TCBR TGRD TGRA TGRB TCNT TSYR Module data bus Internal data bus BUS I/F Control logic Common TSTR A/D converter conversion start signal TGRA TIOR Control logic for channel 0 to 2 TIER TCR TGRB TCNT TIORL TMDR Input/output pins Channel 0: TIOC0A TIOC0B TIOC0C TIOC0D Channel 1: TIOC1A TIOC1B Channel 2: TIOC2A TIOC2B Channel 0 TGRC TIORH Legend: TSTR: TSYR: TCR: TMDR: TIOR (H, L): TIER TCR Timer start register Timer synchro register Timer control register Timer mode register Timer I/O control registers (H, L) TIER: Timer interrupt enable register TSR: Timer status register Timer counter TCNT: TGR (A, B, C, D): Timer general registers (A, B, C, D) Figure 10.1 Block Diagram of MTU Rev. 4.00 Dec 05, 2005 page 136 of 564 REJ09B0270-0400 TGRD TGRA TGRB TCNT Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U TMDR Channel 1 TSR TGRA TIOR TSR TIER TCR TGRB TCNT Section 10 Multi-Function Timer Pulse Unit (MTU) 10.2 Input/Output Pins Table 10.2 MTU Pins Channel Symbol I/O Input Input Input Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function External clock A input pin (Channel 1 phase counting mode A phase input) External clock B input pin (Channel 1 phase counting mode B phase input) External clock C input pin (Channel 2 phase counting mode A phase input) External clock D input pin (Channel 2 phase counting mode B phase input) TGRA_0 input capture input/output compare output/PWM output pin TGRB_0 input capture input/output compare output/PWM output pin TGRC_0 input capture input/output compare output/PWM output pin TGRD_0 input capture input/output compare output/PWM output pin TGRA_1 input capture input/output compare output/PWM output pin TGRB_1 input capture input/output compare output/PWM output pin TGRA_2 input capture input/output compare output/PWM output pin TGRB_2 input capture input/output compare output/PWM output pin TGRA_3 input capture input/output compare output/PWM output pin TGRB_3 input capture input/output compare output/PWM output pin TGRC_3 input capture input/output compare output/PWM output pin TGRD_3 input capture input/output compare output/PWM output pin TGRA_4 input capture input/output compare output/PWM output pin TGRB_4 input capture input/output compare output/PWM output pin TGRC_4 input capture input/output compare output/PWM output pin TGRD_4 input capture input/output compare output/PWM output pin Common TCLKA TCLKB TCLKC TCLKD 0 TIOC0A TIOC0B TIOC0C TIOC0D 1 2 3 TIOC1A TIOC1B TIOC2A TIOC2B TIOC3A TIOC3B TIOC3C TIOC3D 4 TIOC4A TIOC4B TIOC4C TIOC4D Rev. 4.00 Dec 05, 2005 page 137 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.3 Register Descriptions The MTU has the following registers. For details on register addresses and register states during each process, refer to appendix A, Internal I/O Register. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name; TCR for channel 0 is expressed as TCR_0. * Timer control register_0 (TCR_0) * Timer mode register_0 (TMDR_0) * Timer I/O control register H_0 (TIORH_0) * Timer I/O control register L_0 (TIORL_0) * Timer interrupt enable register_0 (TIER_0) * Timer status register_0 (TSR_0) * Timer counter_0 (TCNT_0) * Timer general register A_0 (TGRA_0) * Timer general register B_0 (TGRB_0) * Timer general register C_0 (TGRC_0) * Timer general register D_0 (TGRD_0) * Timer control register_1 (TCR_1) * Timer mode register_1 (TMDR_1) * Timer I/O control register _1 (TIOR_1) * Timer interrupt enable register_1 (TIER_1) * Timer status register_1 (TSR_1) * Timer counter_1 (TCNT_1) * Timer general register A_1 (TGRA_1) * Timer general register B_1 (TGRB_1) * Timer control register_2 (TCR_2) * Timer mode register_2 (TMDR_2) * Timer I/O control register_2 (TIOR_2) * Timer interrupt enable register_2 (TIER_2) * Timer status register_2 (TSR_2) * Timer counter_2 (TCNT_2) * Timer general register A_2 (TGRA_2) * Timer general register B_2 (TGRB_2) * Timer control register_3 (TCR_3) * Timer mode register_3 (TMDR_3) Rev. 4.00 Dec 05, 2005 page 138 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) * Timer I/O control register H_3 (TIORH_3) * Timer I/O control register L_3 (TIORL_3) * Timer interrupt enable register_3 (TIER_3) * Timer status register_3 (TSR_3) * Timer counter_3 (TCNT_3) * Timer general register A_3 (TGRA_3) * Timer general register B_3 (TGRB_3) * Timer general register C_3 (TGRC_3) * Timer general register D_3 (TGRD_3) * Timer control register_4 (TCR_4) * Timer mode register_4 (TMDR_4) * Timer I/O control register H_4 (TIORH_4) * Timer I/O control register L_4 (TIORL_4) * Timer interrupt enable register_4 (TIER_4) * Timer status register_4 (TSR_4) * Timer counter_4 (TCNT_4) * Timer general register A_4 (TGRA_4) * Timer general register B_4 (TGRB_4) * Timer general register C_4 (TGRC_4) * Timer general register D_4 (TGRD_4) Common Registers * Timer start register (TSTR) * Timer synchro register (TSYR) Common Registers for timers 3 and 4 * Timer output master enable register (TOER) * Timer output control enable register (TOCR) * Timer gate control register (TGCR) * Timer cycle data register (TCDR) * Timer dead time data register (TDDR) * Timer subcounter (TCNTS) * Timer cycle buffer register (TCBR) Rev. 4.00 Dec 05, 2005 page 139 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.3.1 Timer Control Register (TCR) The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. The MTU has a total of five TCR registers, one for each channel (channel 0 to 4). TCR register settings should be conducted only when TCNT operation is stopped. Bit 7 6 5 4 3 Bit Name CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 Initial value 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Description Counter Clear 0 to 2 These bits select the TCNT counter clearing source. See tables 10.3 and 10.4 for details. Clock Edge 0 and 1 These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. P/4 both edges = P/2 rising edge). If phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is P/4 or slower. When P/1, or the overflow/underflow of another channel is selected for the input clock, although values can be written, counter operation compiles with the initial value. 00: Count at rising edge 01: Count at falling edge 1X: Count at both edges Legend: X: Don't care 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Time Prescaler 0 to 2 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 10.5 to 10.8 for details. Rev. 4.00 Dec 05, 2005 page 140 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.3 CCLR0 to CCLR2 (channels 0, 3, and 4) Channel 0, 3, 4 Bit 7 CCLR2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* TCNT clearing disabled TCNT cleared by TGRC compare match/input 2 capture* TCNT cleared by TGRD compare match/input 2 capture* TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* 1 0 0 1 1 0 1 Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. Table 10.4 CCLR0 to CCLR2 (channels 1 and 2) Channel 1, 2 Bit 7 Bit 6 2 Reserved* CCLR1 0 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1 and 2. It is always read as 0. Writing is ignored. Rev. 4.00 Dec 05, 2005 page 141 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.5 TPSC0 to TPSC2 (channel 0) Channel 0 Bit 2 TPSC2 0 Bit 1 TPSC1 0 1 1 0 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input Table 10.6 TPSC0 to TPSC2 (channel 1) Channel 1 Bit 2 TPSC2 0 Bit 1 TPSC1 0 1 1 0 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on P/256 Counts on TCNT_2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode. Rev. 4.00 Dec 05, 2005 page 142 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.7 TPSC0 to TPSC2 (channel 2) Channel 2 Bit 2 TPSC2 0 Bit 1 TPSC1 0 1 1 0 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on P/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Table 10.8 TPSC0 to TPSC2 (channels 3 and 4) Channel 3, 4 Bit 2 TPSC2 0 Bit 1 TPSC1 0 1 1 0 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 Internal clock: counts on P/256 Internal clock: counts on P/1024 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Rev. 4.00 Dec 05, 2005 page 143 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.3.2 Timer Mode Register (TMDR) The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode of each channel. The MTU has five TMDR registers, one for each channel. TMDR register settings should be changed only when TCNT operation is stopped. Bit 7, 6 Bit Name Initial value All 1 R/W Description Reserved These bits are always read as 1, and should only be written with 1. 5 BFB 0 R/W Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1 and 2, which have no TGRD, bit 5 is reserved. It is always read as 0, and should only be written with 0. 0: TGRB and TGRD operate normally 1: TGRB and TGRD used together for buffer operation 4 BFA 0 R/W Buffer Operation A Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1 and 2, which have no TGRC, bit 4 is reserved. It is always read as 0, and should only be written with 0. 0: TGRA and TGRC operate normally 1: TGRA and TGRC used together for buffer operation 3 2 1 0 MD3 MD2 MD1 MD0 0 0 0 0 R/W R/W R/W R/W Modes 0 to 3 These bits are used to set the timer operating mode. See table 10.9 for details. Rev. 4.00 Dec 05, 2005 page 144 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.9 MD0 to MD3 Bit 3 MD3 0 Bit 2 MD2 0 Bit 1 MD1 0 1 1 0 1 1 0 0 1 1 0 1 Bit 0 MD0 0 1 0 1 0 1 0 1 0 1 X 0 1 0 1 Description Normal operation Reserved (do not set) PWM mode 1 PWM mode 2* 1 2 Phase counting mode 1* 2 Phase counting mode 2* Phase counting mode 3* 2 Phase counting mode 4* 2 Reset synchronous PWM mode* Reserved (do not set) Reserved (do not set) Reserved (do not set) 3 Complementary PWM mode 1 (transmit at peak)* 3 3 Complementary PWM mode 2 (transmit at bottom)* Complementary PWM mode 2 (transmit at peak and 3 bottom)* Legend: X: Don't care Notes: 1. PWM mode 2 can not be set for channels 3, 4. 2. Phase counting mode can not be set for channels 0, 3, 4. 3. Reset synchronous PWM mode, complementary PWM mode can only be set for channel 3. When channel 3 is set to reset synchronous PWM mode or complementary PWM mode, the channel 4 settings become ineffective and automatically conform to the channel 3 settings. However, do not set channel 4 to reset synchronous PWM mode or complementary PWM mode. Reset synchronous PWM mode and complementary PWM mode can not be set for channels 0, 1, 2. Rev. 4.00 Dec 05, 2005 page 145 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.3.3 Timer I/O Control Register (TIOR) The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU has eight TIOR registers, two each for channels 0, 3, and 4, and one each for channels 1 and 2. Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4 Bit 7 6 5 4 Bit Name IOB3 IOB2 IOB1 IOB0 Initial value 0 0 0 0 R/W R/W R/W R/W R/W Description I/O Control B0 to B3 Specify the function of TGRB. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: Table 10.10 Table 10.14 Table 10.16 Table 10.18 Table 10.22 3 2 1 0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 R/W R/W R/W R/W I/O Control A0 to A3 Specify the function of TGRA. See the following tables. TIORH_0: TIOR_1: TIOR_2: TIORH_3: TIORH_4: Table 10.11 Table 10.15 Table 10.17 Table 10.19 Table 10.23 Rev. 4.00 Dec 05, 2005 page 146 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) TIORL_0, TIORL_3, TIORL_4 Bit 7 6 5 4 Bit Name IOD3 IOD2 IOD1 IOD0 Initial value 0 0 0 0 R/W R/W R/W R/W R/W Description I/O Control D0 to D3 Specify the function of TGRD. When TGRD is used as the buffer register of TGRB, this setting is disabled, and input capture/output compare does not occur. See the following tables. TIORL_0: Table 10.12 TIORL_3: Table 10.20 TIORL_4: Table 10.24 3 2 1 0 IOC3 IOC2 IOC1 IOC0 0 0 0 0 R/W R/W R/W R/W I/O Control C0 to C3 Specify the function of TGRC. When TGRC is used as the buffer register of TGRA, this setting is disabled, and input capture/output compare does not occur. See the following tables. TIORL_0: Table 10.13 TIORL_3: Table 10.21 TIORL_4: Table 10.25 Rev. 4.00 Dec 05, 2005 page 147 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.10 TIORH_0 (channel 0) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X Input capture register TGRB_0 Function Output compare register TIOC0B Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count- up/count-down Legend: X: Don't care Note: * The low level output is retained until TIOR contents is specified after a power-on reset. Rev. 4.00 Dec 05, 2005 page 148 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.11 TIORH_0 (channel 0) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X Input capture register TGRA_0 Function Output compare register TIOC0A Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down Legend: X: Don't care Note: * The low level output is retained until TIOR contents is specified after a power-on reset. Rev. 4.00 Dec 05, 2005 page 149 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.12 TIORL_0 (channel 0) Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 1 1 X 0 1 X X Input capture 2 register* TGRD_0 Function Output compare register TIOC0D Pin Function 1 Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down Legend: X: Don't care Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 4.00 Dec 05, 2005 page 150 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.13 TIORL_0 (channel 0) Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X Input capture 2 register* TGRC_0 Function Output compare register TIOC0C Pin Function 1 Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down Legend: X: Don't care Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset. 2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 4.00 Dec 05, 2005 page 151 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.14 TIOR_1 (channel 1) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 1 1 X 0 1 X X Input capture register TGRB_1 Function Output compare register TIOC1B Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at generation of TGRC_0 compare match/input capture Legend: X: Don't care Note: * The low level output is retained until TIOR contents is specified after a power-on reset. Rev. 4.00 Dec 05, 2005 page 152 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.15 TIOR_1 (channel 1) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 X X X Input capture register TGRA_1 Function Output compare register TIOC1A Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at generation of channel 0/TGRA_0 compare match/input capture Legend: X: Don't care Note: * The low level output is retained until TIOR contents is specified after a power-on reset. Rev. 4.00 Dec 05, 2005 page 153 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.16 TIOR_2 (channel 2) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 1 0 1 X Input capture register TGRB_2 Function Output compare register TIOC2B Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: X: Don't care Note: * The low level output is retained until TIOR contents is specified after a power-on reset. Rev. 4.00 Dec 05, 2005 page 154 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.17 TIOR_2 (channel 2) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X Input capture register TGRA_2 Function Output compare register TIOC2A Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: X: Don't care Note: * The low level output is retained until TIOR contents is specified after a power-on reset. Rev. 4.00 Dec 05, 2005 page 155 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.18 TIORH_3 (channel 3) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X Input capture register TGRB_3 Function Output compare register TIOC3B Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: X: Don't care Note: * The low level output is retained until TIOR contents is specified after a power-on reset. Rev. 4.00 Dec 05, 2005 page 156 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.19 TIORH_3 (channel 3) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X Input capture register TGRA_3 Function Output compare register TIOC3A Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: X: Don't care Note: * The low level output is retained until TIOR contents is specified after a power-on reset. Rev. 4.00 Dec 05, 2005 page 157 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.20 TIORL_3 (channel 3) Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X Input capture 2 register* TGRD_3 Function Output compare register TIOC3D Pin Function 1 Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: X: Don't care Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 4.00 Dec 05, 2005 page 158 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.21 TIORL_3 (channel 3) Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X Input capture 2 register* TGRC_3 Function Output compare register TIOC3C Pin Function 1 Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: X: Don't care Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset. 2. When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 4.00 Dec 05, 2005 page 159 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.22 TIORH_4 (channel 4) Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X Input capture register TGRB_4 Function Output compare register TIOC4B Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: X: Don't care Note: * The low level output is retained until TIOR contents is specified after a power-on reset. Rev. 4.00 Dec 05, 2005 page 160 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.23 TIORH_4 (channel 4) Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X Input capture register TGRA_4 Function Output compare register TIOC4A Pin Function Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: X: Don't care Note: * The low level output is retained until TIOR contents is specified after a power-on reset. Rev. 4.00 Dec 05, 2005 page 161 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.24 TIORL_4 (channel 4) Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X Input capture 2 register* TGRD_4 Function Output compare register TIOC4D Pin Function 1 Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: X: Don't care Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset. 2. When the BFB bit in TMDR_4 is set to 1 and TGRC_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 4.00 Dec 05, 2005 page 162 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.25 TIORL_4 (channel 4) Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 1 1 0 1 1 0 0 1 1 0 1 1 X 0 0 1 1 X Input capture 2 register* TGRC_4 Function Output compare register TIOC4C Pin Function 1 Output hold* Initial output is 0 0 output at compare match Initial output is 0 1 output at compare match Initial output is 0 Toggle output at compare match Output hold Initial output is 1 0 output at compare match Initial output is 1 1 output at compare match Initial output is 1 Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Legend: X: Don't care Notes: 1. The low level output is retained until TIOR contents is specified after a power-on reset. 2. When the BFA bit in TMDR_4 is set to 1 and TGRC_4 is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Rev. 4.00 Dec 05, 2005 page 163 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.3.4 Timer Interrupt Enable Register (TIER) The TIER registers are 8-bit readable/writable registers that control enabling or disabling of interrupt requests for each channel. The MTU has five TIER registers, one for each channel. Bit 7 Bit Name TTGE Initial value 0 R/W R/W Description A/D Conversion Start Request Enable Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled 6 1 R Reserved This bit is always read as 1, and should only be written with 1. 5 TCIEU 0 R/W Underflow Interrupt Enable Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0, and should only be written with 0. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled 4 TCIEV 0 R/W Overflow Interrupt Enable Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled 3 TGIED 0 R/W TGR Interrupt Enable D Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 3 is reserved. It is always read as 0, and should only be written with 0. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled Rev. 4.00 Dec 05, 2005 page 164 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Initial value 0 Bit 2 Bit Name TGIEC R/W R/W Description TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 2 is reserved. It is always read as 0, and should only be written with 0. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled 1 TGIEB 0 R/W TGR Interrupt Enable B Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled 0 TGIEA 0 R/W TGR Interrupt Enable A Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled Rev. 4.00 Dec 05, 2005 page 165 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.3.5 Timer Status Register (TSR) The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The MTU has five TSR registers, one for each channel. Bit 7 Bit Name TCFD Initial value 1 R/W R Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 3, and 4. In channel 0, bit 7 is reserved. It is always read as 1, and should only be written with 1. 0: TCNT counts down 1: TCNT counts up 6 1 R Reserved This bit is always read as 1, and should only be written with 1. 5 TCFU 0 R/(W) Underflow Flag Status flag that indicates that TCNT underflow has occurred when channels 1 and 2 are set to phase counting mode. Only 0 can be written, for flag clearing. In channels 0, 3, and 4, bit 5 is reserved. It is always read as 0, and should only be written with 0. [Setting condition] * When the TCNT value underflows (changes from H'0000 to H'FFFF) When 0 is written to TCFU after reading TCFU = 1 [Clearing condition] * Rev. 4.00 Dec 05, 2005 page 166 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Initial value 0 Bit 4 Bit Name TCFV R/W R/(W) Description Overflow Flag Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Setting condition] * * When the TCNT value overflows (changes from H'FFFF to H'0000 ) In channel 4, when TCNT-4 is underflowed (H'0001 H'0000) in complementary PWM mode. When 0 is written to TCFV after reading TCFV = 1 In channel 4, when DTC is activated by the TCIV interrupt and the DISEL bit in DTMR of DTC is 0. [Clearing condition] * * 3 TGFD 0 R/(W) Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 3 is reserved. It is always read as 0, and should only be written with 0. [Setting conditions] * * When TCNT = TGRD and TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal and TGRD is functioning as input capture register When DTC is activated by TGID interrupt and the DISEL bit of DTMR in DTC is 0 When 0 is written to TGFD after reading TGFD = 1 [Clearing conditions] * * Rev. 4.00 Dec 05, 2005 page 167 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Initial value 0 Bit 2 Bit Name TGFC R/W R/(W) Description Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 2 is reserved. It is always read as 0, and should only be written with 0. [Setting conditions] * * When TCNT = TGRC and TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal and TGRC is functioning as input capture register When DTC is activated by TGIC interrupt and the DISEL bit of DTMR in DTC is 0 When 0 is written to TGFC after reading TGFC = 1 [Clearing conditions] * * 1 TGFB 0 R/(W) Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] * * When TCNT = TGRB and TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal and TGRB is functioning as input capture register When DTC is activated by TGIB interrupt and the DISEL bit of DTMR in DTC is 0 When 0 is written to TGFB after reading TGFB = 1 [Clearing conditions] * * Rev. 4.00 Dec 05, 2005 page 168 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Initial value 0 Bit 0 Bit Name TGFA R/W R/(W) Description Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] * * When TCNT = TGRA and TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal and TGRA is functioning as input capture register When DTC is activated by TGIA interrupt and the DISEL bit of DTMR in DTC is 0 When 0 is written to TGFA after reading TGFA = 1 [Clearing conditions] * * 10.3.6 Timer Counter (TCNT) The TCNT registers are 16-bit readable/writable counters. The MTU has five TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 10.3.7 Timer General Register (TGR) The TGR registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture registers. The MTU has 16 TGR registers, four each for channels 0, 3, and 4 and two each for channels 1 and 2. TGRC and TGRD for channels 0, 3, and 4 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. TGR buffer register combinations are TGRATGRC and TGRBTGRD. The initial value of TGR is H'FFFF. Rev. 4.00 Dec 05, 2005 page 169 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.3.8 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 4. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bit 7 6 Bit Name CST4 CST3 Initial value 0 0 R/W R/W R/W Description Counter Start 4 and 3 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_4 and TCNT_3 count operation is stopped 1: TCNT_4 and TCNT_3 performs count operation 5 to 3 All 0 R Reserved These bits are always read as 0. Only 0 should be written to these bits. 2 1 0 CST2 CST1 CST0 0 0 0 R/W R/W R/W Counter Start 2 to 0 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_2 to TCNT_0 count operation is stopped 1: TCNT_2 to TCNT_0 performs count operation 10.3.9 Timer Synchro Register (TSYR) TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. Rev. 4.00 Dec 05, 2005 page 170 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Initial value 0 0 Bit 7 6 Bit Name SYNC4 SYNC3 R/W R/W R/W Description Timer Synchro 4 and 3 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_4 and TCNT_3 operate independently (TCNT presetting/clearing is unrelated to other channels) 1: TCNT_4 and TCNT_3 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible 5 to 3 All 0 R Reserved These bits are always read as 0. Only 0 should be written to these bits. 2 1 0 SYNC2 SYNC1 SYNC0 0 0 0 R/W R/W R/W Timer Synchro 2 to 0 These bits are used to select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR0 to CCLR2 in TCR. 0: TCNT_2 to TCNT_0 operates independently (TCNT presetting /clearing is unrelated to other channels) 1: TCNT_2 to TCNT_0 performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible Rev. 4.00 Dec 05, 2005 page 171 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.3.10 Timer Output Master Enable Register (TOER) TOER is an 8-bit readable/writable register that enables/disables output settings for output pins TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly if the TOER bits have not been set. Set TOER of CH3 and CH4 prior to setting TIOR of CH3 and CH4. Bit 7, 6 Bit Name Initial value All 1 R/W R Description Reserved These bits are always read as 1. Only 1 should be written to these bits. 5 OE4D 0 R/W Master Enable TIOC4D This bit enables/disables the TIOC4D pin MTU output. 0: MTU output is disabled 1: MTU output is enabled 4 OE4C 0 R/W Master Enable TIOC4C This bit enables/disables the TIOC4C pin MTU output. 0: MTU output is disabled 1: MTU output is enabled 3 OE3D 0 R/W Master Enable TIOC3D This bit enables/disables the TIOC3D pin MTU output. 0: MTU output is disabled 1: MTU output is enabled 2 OE4B 0 R/W Master Enable TIOC4B This bit enables/disables the TIOC4B pin MTU output. 0: MTU output is disabled 1: MTU output is enabled 1 OE4A 0 R/W Master Enable TIOC4A This bit enables/disables the TIOC4A pin MTU output. 0: MTU output is disabled 1: MTU output is enabled 0 OE3B 0 R/W Master Enable TIOC3B This bit enables/disables the TIOC3B pin MTU output. 0: MTU output is disabled 1: MTU output is enabled Rev. 4.00 Dec 05, 2005 page 172 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.3.11 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that enables/disables PWM synchronized toggle output in complementary PWM mode/reset synchronized PWM mode, and controls output level inversion of PWM output. Bit 7 Bit Name Initial value 0 R/W R Description Reserved This bit is always read as 0. Only 0 should be written to this bit. 6 PSYE 0 R/W PWM Synchronous Output Enable This bit selects the enable/disable of toggle output synchronized with the PWM period. 0: Toggle output is disabled 1: Toggle output is enabled 5 to 2 All 0 R Reserved These bits are always read as 0. Only 0 should be written to this bit. 1 OLSN 0 R/W Output Level Select N This bit selects the reverse phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 10.26 0 OLSP 0 R/W Output Level Select P This bit selects the positive phase output level in resetsynchronized PWM mode/complementary PWM mode. See table 10.27 Table 10.26 Output Level Select Function Bit 1 OLSN 0 1 Initial Output High level Low level Active Level Low level High level Function Compare Match Output Increment Count High level Low level Decrement Count Low level High level Note: The reverse phase waveform initial output value changes to active level after elapse of the dead time after count start. Rev. 4.00 Dec 05, 2005 page 173 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.27 Output Level Select Function Bit 1 OLSP 0 1 Initial Output High level Low level Active Level Low level High level Function Compare Match Output Increment Count Low level High level Decrement Count High level Low level Figure 10.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1, OLSP = 1. TCNT_3, and TCNT_4 values TGRA_3 TCNT_3 TCNT_4 TGRA_4 TDDR H'0000 Initial output Initial output Active level Compare match output (up count) Active level Compare match output (down count) Compare match output (down count) Compare match output (up count) Active level Time Positive phase output Reverse phase output Figure 10.2 Complementary PWM Mode Output Level Example 10.3.12 Timer Gate Control Register (TGCR) TGCR is an 8-bit readable/writable register that controls the waveform output necessary for brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These register settings are ineffective for anything other than complementary PWM mode/resetsynchronized PWM mode. Rev. 4.00 Dec 05, 2005 page 174 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Initial value 0 Bit 7 Bit Name R/W R Description Reserved This bit is always read as 1. Only 1 should be written to this bit. 6 BDC 0 R/W Brushless DC Motor This bit selects whether to make the functions of this register (TGCR) effective or ineffective. 0: Ordinary output 1: Functions of this register are made effective 5 N 0 R/W Reverse Phase Output (N) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are onoutput. 0: Level output 1: Reset synchronized PWM/complementary PWM output 4 P 0 R/W Positive Phase Output (P) Control This bit selects whether the level output or the resetsynchronized PWM/complementary PWM output while the positive pin (TIOC3B, TIOC4A, and TIOC4B) are onoutput. 0: Level output 1: Reset synchronized PWM/complementary PWM output 3 FB 0 R/W External Feedback Signal Enable This bit selects whether the switching of the output of the positive/reverse phase is carried out automatically with the MTU/channel 0 TGRA, TGRB, TGRC input capture signals or by writing 0 or 1 to bits 2 to 0 in TGCR. 0: Output switching is carried out by external input (Input sources are channel 0 TGRA, TGRB, TGRC input capture signal) 1: Output switching is carried out by software (TGCR's UF, VF, WF settings). 2 1 0 WF VF UF 0 0 0 R/W R/W R/W Output Phase Switch 2 to 0 These bits set the positive phase/negative phase output phase on or off state. The setting of these bits is valid only when the FB bit in this register is set to 1. In this case, the setting of bits 2 to 0 is a substitute for external input. See table 10.28. Rev. 4.00 Dec 05, 2005 page 175 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.28 Output level Select Function Function Bit 2 WF 0 Bit 1 VF 0 1 1 0 1 Bit 0 UF 0 1 0 1 0 1 0 1 TIOC3B U Phase OFF ON OFF OFF OFF ON OFF OFF TIOC4A V Phase OFF OFF ON ON OFF OFF OFF OFF TIOC4B TIOC3D TIOC4C V Phase OFF OFF OFF OFF ON ON OFF OFF TIOC4D W Phase OFF ON OFF ON OFF OFF OFF OFF W Phase U Phase OFF OFF OFF OFF ON OFF ON OFF OFF OFF ON OFF OFF OFF ON OFF 10.3.13 Timer Subcounter (TCNTS) TCNTS is a 16-bit read-only counter that is used only in complementary PWM mode. The initial value is H'0000. Note: Accessing the TCNTS in 8-bit units is prohibited. Always access in 16-bit units. 10.3.14 Timer Dead Time Data Register (TDDR) TDDR is a 16-bit register, used only in complementary PWM mode, that specifies the TCNT_3 and TCNT_4 counter offset values. In complementary PWM mode, when the TCNT_3 and TCNT_4 counters are cleared and then restarted, the TDDR register value is loaded into the TCNT_3 counter and the count operation starts. The initial value is H'FFFF. Note: Accessing the TDDR in 8-bit units is prohibited. Always access in 16-bit units. 10.3.15 Timer Period Data Register (TCDR) TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier sync value as the TCDR register value. This register is constantly compared with the TCNTS counter in complementary PWM mode, and when a match occurs, the TCNTS counter switches direction (decrement to increment). The initial value is H'FFFF. Note: Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units. Rev. 4.00 Dec 05, 2005 page 176 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.3.16 Timer Period Buffer Register (TCBR) The timer period buffer register (TCBR) is a 16-bit register used only in complementary PWM mode. It functions as a buffer register for the TCDR register. The TCBR register values are transferred to the TCDR register with the transfer timing set in the TMDR register. The initial value is H'FFFF. Note: Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units. 10.3.17 Bus Master Interface The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer period buffer register (TCBR), and timer dead time data register (TDDR), and timer period data register (TCDR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8-bit read/write is not possible. Always access in 16-bit units. All registers other than the above registers are 8-bit registers. These are connected to the CPU by a 16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible. Rev. 4.00 Dec 05, 2005 page 177 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.4 10.4.1 Operation Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Always set the MTU external pins function using the pin function controller (PFC). Counter Operation When one of bits CST0 to CST4 is set to 1 in TSTR, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. Example of Count Operation Setting Procedure: Figure 10.3 shows an example of the count operation setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Free-running counter [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Start count operation Operation selection Select counter clock [1] Periodic counter Select counter clearing source Select output compare register Set period [2] [3] [4] [5] Start count operation Figure 10.3 Example of Counter Operation Setting Procedure Rev. 4.00 Dec 05, 2005 page 178 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Free-Running Count Operation and Periodic Count Operation: Immediately after a reset, the MTU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the MTU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 10.4 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 10.4 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR0 to CCLR2 in TCR. After the settings have been made, TCNT starts up-count operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. Figure 10.5 illustrates periodic counter operation. Rev. 4.00 Dec 05, 2005 page 179 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) TCNT value TGR Counter cleared by TGR compare match H'0000 Time CST bit Flag cleared by software or DTC activation TGF Figure 10.5 Periodic Counter Operation Waveform Output by Compare Match The MTU can perform 0, 1, or toggle output from the corresponding output pin using compare match. Example of Setting Procedure for Waveform Output by Compare Match: Figure 10.6 shows an example of the setting procedure for waveform output by compare match Output selection Select waveform output mode [1] [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. Set output timing [2] [3] Set the CST bit in TSTR to 1 to start the count operation. Start count operation [3] Figure 10.6 Example of Setting Procedure for Waveform Output by Compare Match Rev. 4.00 Dec 05, 2005 page 180 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Examples of Waveform Output Operation: Figure 10.7 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB H'0000 TIOCA TIOCB No change No change Time No change No change 1 output 0 output Figure 10.7 Example of 0 Output/1 Output Operation Figure 10.8 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 TIOCB TIOCA Time Toggle output Toggle output Figure 10.8 Example of Toggle Output Operation Rev. 4.00 Dec 05, 2005 page 181 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Input Capture Function The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0 and 1, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 1, /1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if /1 is selected. Example of Input Capture Operation Setting Procedure: Figure 10.9 shows an example of the input capture operation setting procedure. [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] Set the CST bit in TSTR to 1 to start the count operation. Input selection Select input capture input [1] Start count [2] Figure 10.9 Example of Input Capture Operation Setting Procedure Example of Input Capture Operation: Figure 10.10 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. Rev. 4.00 Dec 05, 2005 page 182 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) TCNT value H'0180 H'0160 Counter cleared by TIOCB input (falling edge) H'0010 H'0005 H'0000 Time TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 10.10 Example of Input Capture Operation 10.4.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 4 can all be designated for synchronous operation. Rev. 4.00 Dec 05, 2005 page 183 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Example of Synchronous Operation Setting Procedure: Figure 10.11 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Synchronous clearing Set TCNT [2] Clearing source generation channel? Yes Select counter clearing source [3] Set synchronous counter clearing [4] No Start count [5] Start count [5] [1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 10.11 Example of Synchronous Operation Setting Procedure Rev. 4.00 Dec 05, 2005 page 184 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Example of Synchronous Operation: Figure 10.12 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details of PWM modes, see section 10.4.5, PWM Modes. Synchronous clearing by TGRB_0 compare match TCNT0 to TCNT2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 TIOCA_0 TIOCA_1 TIOCA_2 Time Figure 10.12 Example of Synchronous Operation 10.4.3 Buffer Operation Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 10.29 shows the register combinations used in buffer operation. Rev. 4.00 Dec 05, 2005 page 185 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.29 Register Combinations in Buffer Operation Channel 0 3 4 Timer General Register TGRA_0 TGRB_0 TGRA_3 TGRB_3 TGRA_4 TGRB_4 Buffer Register TGRC_0 TGRD_0 TGRC_3 TGRD_3 TGRC_4 TGRD_4 * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 10.13. Compare match signal Buffer register Timer general register Comparator TCNT Figure 10.13 Compare Match Buffer Operation * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 10.14. Input capture signal Buffer register Timer general register TCNT Figure 10.14 Input Capture Buffer Operation Rev. 4.00 Dec 05, 2005 page 186 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Example of Buffer Operation Setting Procedure: Figure 10.15 shows an example of the buffer operation setting procedure. [1] Designate TGR as an input capture register or output compare register by means of TIOR. [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 start the count operation. Set buffer operation [2] Buffer operation Select TGR function [1] Start count [3] Figure 10.15 Example of Buffer Operation Setting Procedure Examples of Buffer Operation: * When TGR is an output compare register Figure 10.16 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time that compare match A occurs. For details of PWM modes, see section 10.4.5, PWM Modes. Rev. 4.00 Dec 05, 2005 page 187 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) TCNT value TGRB_0 H'0200 TGRA_0 H'0000 TGRC_0 H'0200 Transfer TGRA_0 H'0200 H'0450 H'0450 H'0520 Time H'0520 H'0450 TIOCA Figure 10.16 Example of Buffer Operation (1) * When TGR is an input capture register Figure 10.17 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon the occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. Rev. 4.00 Dec 05, 2005 page 188 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 H'0F07 H'0532 H'09FB H'0F07 TGRC Figure 10.17 Example of Buffer Operation (2) 10.4.4 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 counter clock upon overflow/underflow of TCNT_2 as set in bits TPSC0 to TPSC2 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 10.30 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counters operates independently in phase counting mode. Table 10.30 Cascaded Combinations Combination Channels 1 and 2 Upper 16 Bits TCNT_1 Lower 16 Bits TCNT_2 Rev. 4.00 Dec 05, 2005 page 189 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Example of Cascaded Operation Setting Procedure: Figure 10.18 shows an example of the setting procedure for cascaded operation. Cascaded operation [1] Set bits TPSC2 to TPSC0 in the channel 1 TCR to B'1111 to select TCNT_2 overflow/ underflow counting. [1] [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Set cascading Start count [2] Figure 10.18 Cascaded Operation Setting Procedure Examples of Cascaded Operation: Figure 10.19 illustrates the operation when TCNT_2 overflow/underflow counting has been set for TCNT_1 and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow. TCLKC TCLKD TCNT_2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF TCNT_1 0000 0001 0000 Figure 10.19 Example of Cascaded Operation Rev. 4.00 Dec 05, 2005 page 190 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. * PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. * PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 8-phase PWM output is possible in combination use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 10.31. Rev. 4.00 Dec 05, 2005 page 191 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.31 PWM Output Registers and Output Pins Output Pins Channel 0 Registers TGRA_0 TGRB_0 TGRC_0 TGRD_0 1 2 3 TGRA_1 TGRB_1 TGRA_2 TGRB_2 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TGRA_4 TGRB_4 TGRC_4 TGRD_4 TIOC4C TIOC4A TIOC3C TIOC3A TIOC2A TIOC1A TIOC0C PWM Mode 1 TIOC0A PWM Mode 2 TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A TIOC1B TIOC2A TIOC2B Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Cannot be set Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. Rev. 4.00 Dec 05, 2005 page 192 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Example of PWM Mode Setting Procedure: Figure 10.20 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [3] [4] Set the cycle in the TGR selected in [2], and set the duty in the other TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 to start the count operation. Set PWM mode [5] PWM mode Select counter clock [1] Select counter clearing source [2] Select waveform output level Set TGR [4] Start count [6] Figure 10.20 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation: Figure 10.21 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in the TGRB registers are used as the duty cycle. Rev. 4.00 Dec 05, 2005 page 193 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 TIOCA Time Figure 10.21 Example of PWM Mode Operation (1) Figure 10.22 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs are used as the duty levels. Counter cleared by TGRB_1 compare match TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 Time TIOC0A TIOC0B TIOC0C TIOC0D TIOC1A Figure 10.22 Example of PWM Mode Operation (2) Rev. 4.00 Dec 05, 2005 page 194 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Figure 10.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode. TCNT value TGRB rewritten TGRA TGRB H'0000 TGRB rewritten TGRB rewritten Time TIOCA 0% duty cycle Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty cycle TGRB rewritten Time TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty cycle 0% duty cycle TGRB rewritten Time TIOCA Figure 10.23 Example of PWM Mode Operation (3) Rev. 4.00 Dec 05, 2005 page 195 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT counts up or down accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR. However, the functions of bits CCLR0 and CCLR1 in TCR, and of TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs when TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is counting up or down. Table 10.32 shows the correspondence between external clock pins and channels. Table 10.32 Phase Counting Mode Clock Input Pins External Clock Pins Channels When channel 1 is set to phase counting mode When channel 2 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD Example of Phase Counting Mode Setting Procedure: Figure 10.24 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Phase counting mode Select phase counting mode [1] Start count [2] Figure 10.24 Example of Phase Counting Mode Setting Procedure Rev. 4.00 Dec 05, 2005 page 196 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. * Phase counting mode 1 Figure 10.25 shows an example of phase counting mode 1 operation, and table 10.33 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 10.25 Example of Phase Counting Mode 1 Operation Table 10.33 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Down-count TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count Rev. 4.00 Dec 05, 2005 page 197 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) * Phase counting mode 2 Figure 10.26 shows an example of phase counting mode 2 operation, and table 10.34 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 10.26 Example of Phase Counting Mode 2 Operation Table 10.34 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Operation Don't care Don't care Don't care Up-count Don't care Don't care Don't care Down-count Rev. 4.00 Dec 05, 2005 page 198 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) * Phase counting mode 3 Figure 10.27 shows an example of phase counting mode 3 operation, and table 10.35 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count Down-count Time Figure 10.27 Example of Phase Counting Mode 3 Operation Table 10.35 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge TCLKB (Channel 1) TCLKD (Channel 2) Operation Don't care Don't care Don't care Up-count Down-count Don't care Don't care Don't care Rev. 4.00 Dec 05, 2005 page 199 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) * Phase counting mode 4 Figure 10.28 shows an example of phase counting mode 4 operation, and table 10.36 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count Up-count Time Figure 10.28 Example of Phase Counting Mode 4 Operation Table 10.36 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channel 1) TCLKC (Channel 2) High level Low level Low level High level High level Low level High level Low level Legend: : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channel 1) TCLKD (Channel 2) Operation Up-count Rev. 4.00 Dec 05, 2005 page 200 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Phase Counting Mode Application Example: Figure 10.29 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control period and position control period. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse widths of 2-phase encoder 4-multiplication pulses are detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, and channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source and store the up/down-counter values for the control periods. This procedure enables the accurate detection of position and speed. Rev. 4.00 Dec 05, 2005 page 201 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed period capture) TGRB_1 (position period capture) TCNT_0 + + - TGRA_0 (speed control period) TGRC_0 (position control period) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 10.29 Phase Counting Mode Application Example Rev. 4.00 Dec 05, 2005 page 202 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.4.7 Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms that share a common wave transition point can be obtained by combining channels 3 and 4. When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, and TIOC4D pins function as PWM output pins and TCNT3 functions as an upcounter. Table 10.37 shows the PWM output pins used. Table 10.38 shows the settings of the registers. Table 10.37 Output Pins for Reset-Synchronized PWM Mode Channel 3 4 Output Pin TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D Description PWM output pin 1 PWM output pin 1' (negative-phase waveform of PWM output 1) PWM output pin 2 PWM output pin 2' (negative-phase waveform of PWM output 2) PWM output pin 3 PWM output pin 3' (negative-phase waveform of PWM output 3) Table 10.38 Register Settings for Reset-Synchronized PWM Mode Register TCNT_3 TCNT_4 TGRA_3 TGRB_3 TGRA_4 TGRB_4 Description of Setting Initial setting of H'0000 Initial setting of H'0000 Set count cycle for TCNT_3 Sets the turning point for PWM waveform output by the TIOC3B and TIOC3D pins Sets the turning point for PWM waveform output by the TIOC4A and TIOC4C pins Sets the turning point for PWM waveform output by the TIOC4B and TIOC4D pins Rev. 4.00 Dec 05, 2005 page 203 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Procedure for Selecting the Reset-Synchronized PWM Mode: Figure 10.30 shows an example of procedure for selecting the reset synchronized PWM mode. 1. Clear the CST3 and CST4 bits in the TSTR to 0 to halt the counting of TCNT. The resetsynchronized PWM mode must be set up while TCNT_3 and TCNT_4 are halted. 2. Set bits TPSC2-TPSC0 and CKEG1 and CKEG0 in the TCR_3 to select the counter clock and clock edge for channel 3. Set bits CCLR2-CCLR0 in the TCR_3 to select TGRA comparematch as a counter clear source. 3. When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. 4. Reset TCNT_3 and TCNT_4 to H'0000. 5. TGRA_3 is the period register. Set the waveform period value in TGRA_3. Set the transition timing of the PWM output waveforms in TGRB_3, TGRA_4, and TGRB_4. Set times within the compare-match range of TCNT_3. X TGRA_3 (X: set value). 6. Select enabling/disabling of toggle output synchronized with the PMW cycle using bit PSYE in the timer output control register (TOCR), and set the PWM output level with bits OLSP and OLSN. 7. Set bits MD3-MD0 in TMDR_3 to B'1000 to select the reset-synchronized PWM mode. TIOC3A, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C and TIOC4D function as PWM output pins*. Do not set to TMDR_4. 8. Set the enabling/disabling of the PWM waveform output pin in TOER. 9. Set the CST3 bit in the TSTR to 1 to start the count operation. Notes: The output waveform starts to toggle operation at the point of TCNT_3 = TGRA_3 = X by setting X = TGRA, i.e., cycle = duty. * PFC registers should be specified before this procedure. Rev. 4.00 Dec 05, 2005 page 204 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Reset-synchronized PWM mode Stop counting 1 Select counter clock and counter clear source 2 Brushless DC motor control setting 3 Set TCNT 4 Set TGR 5 PWM cycle output enabling, PWM output level setting 6 Set reset-synchronized PWM mode 7 Enable waveform output 8 Start count operation Reset-synchronized PWM mode 9 Figure 10.30 Procedure for Selecting the Reset-Synchronized PWM Mode Rev. 4.00 Dec 05, 2005 page 205 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Reset-Synchronized PWM Mode Operation: Figure 10.31 shows an example of operation in the reset-synchronized PWM mode. TCNT_3 and TCNT_4 operate as upcounters. The counter is cleared when a TCNT_3 and TGRA_3 compare-match occurs, and then begins counting up from H'0000. The PWM output pin output toggles with each occurrence of a TGRB_3, TGRA_4, TGRB_4 compare-match, and upon counter clears. TCNT3 and TCNT4 values TGRA_3 TGRB_3 TGRA_4 TGRB_4 H'0000 Time TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D Figure 10.31 Reset-Synchronized PWM Mode Operation Example (When the TOCR's OLSN = 1 and OLSP = 1) Rev. 4.00 Dec 05, 2005 page 206 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.4.8 Complementary PWM Mode In the complementary PWM mode, three-phase output of non-overlapping positive and negative PWM waveforms can be obtained by combining channels 3 and 4. In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins function as PWM output pins, the TIOC3A pin can be set for toggle output synchronized with the PWM period. TCNT_3 and TCNT_4 function as increment/decrement counters. Table 10.39 shows the PWM output pins used. Table 10.40 shows the settings of the registers used. A function to directly cut off the PWM output by using an external signal is supported as a port function. Table 10.39 Output Pins for Complementary PWM Mode Channel 3 Output Pin TIOC3A TIOC3B TIOC3C TIOC3D 4 TIOC4A TIOC4B TIOC4C TIOC4D Note: * Description Toggle output synchronized with PWM period (or I/O port) PWM output pin 1 I/O port* PWM output pin 1' (non-overlapping negative-phase waveform of PWM output 1) PWM output pin 2 PWM output pin 3 PWM output pin 2' (non-overlapping negative-phase waveform of PWM output 2) PWM output pin 3' (non-overlapping negative-phase waveform of PWM output 3) Avoid setting the TIOC3C pin as a timer I/O pin in the complementary PWM mode. Rev. 4.00 Dec 05, 2005 page 207 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.40 Register Settings for Complementary PWM Mode Channel 3 Counter/Register TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TCNT_4 TGRA_4 TGRB_4 TGRC_4 TGRD_4 Timer dead time data register (TDDR) Timer cycle data register (TCDR) Timer cycle buffer register (TCBR) Subcounter (TCNTS) Temporary register 1 (TEMP1) Temporary register 2 (TEMP2) Temporary register 3 (TEMP3) Note: * Description Start of up-count from value set in dead time register Set TCNT_3 upper limit value (1/2 carrier cycle + dead time) PWM output 1 compare register TGRA_3 buffer register PWM output 1/TGRB_3 buffer register Up-count start, initialized to H'0000 PWM output 2 compare register PWM output 3 compare register PWM output 2/TGRA_4 buffer register PWM output 3/TGRB_4 buffer register Set TCNT_4 and TCNT_3 offset value (dead time value) Set TCNT_4 upper limit value (1/2 carrier cycle) TCDR buffer register Subcounter for dead time generation PWM output 1/TGRB_3 temporary register PWM output 2/TGRA_4 temporary register PWM output 3/TGRB_4 temporary register Read/Write from CPU Maskable by BSC/BCR1 setting* Maskable by BSC/BCR1 setting* Maskable by BSC/BCR1 setting* Always readable/writable Always readable/writable Maskable by BSC/BCR1 setting* Maskable by BSC/BCR1 setting* Maskable by BSC/BCR1 setting* Always readable/writable Always readable/writable Maskable by BSC/BCR1 setting* Maskable by BSC/BCR1 setting* Always readable/writable Read-only Not readable/writable Not readable/writable Not readable/writable Access can be enabled or disabled according to the setting of bit 13 (MTURWE) in BSC/BCR1 (bus controller/bus control register 1). Rev. 4.00 Dec 05, 2005 page 208 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) TCNT_4 underflow interrupt TGRA_3 comparematch interrupt TGRC_3 TCBR TDDR TGRA_3 TCDR Comparator Output controller Match signal PWM cycle output PWM output 1 PWM output 2 PWM output 3 PWM output 4 PWM output 5 PWM output 6 External cutoff input POE0 POE1 POE2 POE3 Comparator Match signal TGRB_3 TGRA_4 TGRD_3 TGRC_4 TGRD_4 TGRB_4 Temp 1 Temp 2 Temp 3 External cutoff interrupt : Registers that can always be read or written from the CPU : Registers that can be read or written from the CPU (but for which access disabling can be set by the bus controller) : Registers that cannot be read or written from the CPU (except for TCNTS, which can only be read) Figure 10.32 Block Diagram of Channels 3 and 4 in Complementary PWM Mode Rev. 4.00 Dec 05, 2005 page 209 of 564 REJ09B0270-0400 Output protection circuit TCNT_3 TCNTS TCNT_4 Section 10 Multi-Function Timer Pulse Unit (MTU) Example of Complementary PWM Mode Setting Procedure: An example of the complementary PWM mode setting procedure is shown in Figure 10.33. 1. Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation. Perform complementary PWM mode setting when TCNT_3 and TCNT_4 are stopped. 2. Set the same counter clock and clock edge for channels 3 and 4 with bits TPSC2-TPSC0 and bits CKEG1 and CKEG0 in the timer control register (TCR). Use bits CCLR2-CCLR0 to set synchronous clearing only when restarting by a synchronous clear from another channel during complementary PWM mode operation. 3. When performing brushless DC motor control, set bit BDC in the timer gate control register (TGCR) and set the feedback signal input source and output chopping or gate signal direct output. 4. Set the dead time in TCNT_3. Set TCNT_4 to H'0000. 5. Set only when restarting by a synchronous clear from another channel during complementary PWM mode operation. In this case, synchronize the channel generating the synchronous clear with channels 3 and 4 using the timer synchro register (TSYR). 6. Set the output PWM duty in the duty registers (TGRB_3, TGRA_4, TGRB_4) and buffer registers (TGRD_3, TGRC_4, TGRD_4). Set the same initial value in each corresponding TGR. 7. Set the dead time in the dead time register (TDDR), 1/2 the carrier cycle in the carrier cycle data register (TCDR) and carrier cycle buffer register (TCBR), and 1/2 the carrier cycle plus the dead time in TGRA_3 and TGRC_3. 8. Select enabling/disabling of toggle output synchronized with the PWM cycle using bit PSYE in the timer output control register (TOCR), and set the PWM output level with bits OLSP and OLSN. 9. Select complementary PWM mode in timer mode register 3 (TMDR_3). Pins TIOC3A, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D function as output pins*. Do not set in TMDR_4. 10. Set enabling/disabling of PWM waveform output pin output in the timer output master enable register (TOER). 11. Set the port control and port I/O registers. 12. Set bits CST3 and CST4 in TSTR to 1 simultaneously to start the count operation. Note: * PFC registers should be specified before this procedure. Rev. 4.00 Dec 05, 2005 page 210 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Complementary PWM mode Stop count operation 1 Counter clock, counter clear source selection 2 Brushless DC motor control setting 3 TCNT setting 4 Inter-channel synchronization setting 5 TGR setting 6 Dead time, carrier cycle setting PWM cycle output enabling, PWM output level setting Complementary PWM mode setting 7 8 9 Enable waveform output 10 Start count operation 11 Figure 10.33 Example of Complementary PWM Mode Setting Procedure Rev. 4.00 Dec 05, 2005 page 211 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Outline of Complementary PWM Mode Operation In complementary PWM mode, 6-phase PWM output is possible. Figure 10.34 illustrates counter operation in complementary PWM mode, and Figure 10.35 shows an example of complementary PWM mode operation. Counter Operation: In complementary PWM mode, three countersTCNT_3, TCNT_4, and TCNTSperform up/down-count operations. TCNT_3 is automatically initialized to the value set in TDDR when complementary PWM mode is selected and the CST bit in TSTR is 0. When the CST bit is set to 1, TCNT_3 counts up to the value set in TGRA_3, then switches to down-counting when it matches TGRA_3,. When the TCNT3 value matches TDDR, the counter switches to up-counting, and the operation is repeated in this way. TCNT_4 is initialized to H'0000. When the CST bit is set to 1, TCNT4 counts up in synchronization with TCNT_3, and switches to down-counting when it matches TCDR . On reaching H'0000, TCNT4 switches to up-counting, and the operation is repeated in this way. TCNTS is a read-only counter. It need not be initialized. When TCNT_3 matches TCDR during TCNT_3 and TCNT_4 up/down-counting, down-counting is started, and when TCNTS matches TCDR, the operation switches to up-counting. When TCNTS matches TGRA_3, it is cleared to H'0000. When TCNT_4 matches TDDR during TCNT_3 and TCNT_4 down-counting, up-counting is started, and when TCNTS matches TDDR, the operation switches to down-counting. When TCNTS reaches H'0000, it is set with the value in TGRA_3. TCNTS is compared with the compare register and temporary register in which the PWM duty is set during the count operation only. Rev. 4.00 Dec 05, 2005 page 212 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) TCNT_3 TCNT_4 TCNTS Counter value TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Time TCNTS Figure 10.34 Complementary PWM Mode Counter Operation Register Operation: In complementary PWM mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. Figure 10.35 shows an example of complementary PWM mode operation. The registers which are constantly compared with the counters to perform PWM output are TGRB_3, TGRA_4, and TGRB_4. When these registers match the counter, the value set in bits OLSN and OLSP in the timer output control register (TOCR) is output. The buffer registers for these compare registers are TGRD_3, TGRC_4, and TGRD_4. Between a buffer register and compare register there is a temporary register. The temporary registers cannot be accessed by the CPU. Data in a compare register is changed by writing the new data to the corresponding buffer register. The buffer registers can be read or written at any time. The data written to a buffer register is constantly transferred to the temporary register in the Ta interval. Data is not transferred to the temporary register in the Tb interval. Data written to a buffer register in this interval is transferred to the temporary register at the end of the Tb interval. The value transferred to a temporary register is transferred to the compare register when TCNTS for which the Tb interval ends matches TGRA_3 when counting up, or H'0000 when counting down. The timing for transfer from the temporary register to the compare register can be selected with bits MD3-MD0 in the timer mode register (TMDR). Figure 10.35 shows an example in which the mode is selected in which the change is made in the trough. Rev. 4.00 Dec 05, 2005 page 213 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) In the tb interval (tb1 in Figure 10.35) in which data transfer to the temporary register is not performed, the temporary register has the same function as the compare register, and is compared with the counter. In this interval, therefore, there are two compare match registers for one-phase output, with the compare register containing the pre-change data, and the temporary register containing the new data. In this interval, the three countersTCNT_3, TCNT_4, and TCNTSand two registerscompare register and temporary registerare compared, and PWM output controlled accordingly. Rev. 4.00 Dec 05, 2005 page 214 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Transfer from temporary register to compare register Transfer from temporary register to compare register Tb2 TGRA_3 Ta Tb1 Ta Tb2 Ta TCNTS TCDR TCNT_3 TGRA_4 TCNT_4 TGRC_4 TDDR H'0000 Buffer register TGRC_4 Temporary register TEMP2 H'6400 H'0080 H'6400 H'0080 Compare register TGRA_4 H'6400 H'0080 Output waveform Output waveform (Output waveform is active-low) Figure 10.35 Example of Complementary PWM Mode Operation Rev. 4.00 Dec 05, 2005 page 215 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Initialization: In complementary PWM mode, there are six registers that must be initialized. Before setting complementary PWM mode with bits MD3-MD0 in the timer mode register (TMDR), the following initial register values must be set. TGRC_3 operates as the buffer register for TGRA_3, and should be set with 1/2 the PWM carrier cycle + dead time Td. The timer cycle buffer register (TCBR) operates as the buffer register for the timer cycle data register (TCDR), and should be set with 1/2 the PWM carrier cycle. Set dead time Td in the timer dead time data register (TDDR). Set the respective initial PWM duty values in buffer registers TGRD_3, TGRC_4, and TGRD_4. The values set in the five buffer registers excluding TDDR are transferred simultaneously to the corresponding compare registers when complementary PWM mode is set. Set TCNT_4 to H'0000 before setting complementary PWM mode. Table 10.41 Registers and Counters Requiring Initialization Register/Counter TGRC_3 TDDR TCBR TGRD_3, TGRC_4, TGRD_4 TCNT_4 Set Value 1/2 PWM carrier cycle + dead time Td Dead time Td 1/2 PWM carrier cycle Initial PWM duty value for each phase H'0000 Note: The TGRC_3 set value must be the sum of 1/2 the PWM carrier cycle set in TCBR and dead time Td set in TDDR. PWM Output Level Setting: In complementary PWM mode, the PWM pulse output level is set with bits OLSN and OLSP in the timer output control register (TOCR). The output level can be set for each of the three positive phases and three negative phases of 6phase output. Complementary PWM mode should be cleared before setting or changing output levels. Dead Time Setting: In complementary PWM mode, PWM pulses are output with a nonoverlapping relationship between the positive and negative phases. This non-overlap time is called the dead time. Rev. 4.00 Dec 05, 2005 page 216 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) The non-overlap time is set in the timer dead time data register (TDDR). The value set in TDDR is used as the TCNT_3 counter start value, and creates non-overlap between TCNT_3 and TCNT_4. Complementary PWM mode should be cleared before changing the contents of TDDR. PWM Cycle Setting: In complementary PWM mode, the PWM pulse cycle is set in two registersTGRA_3, in which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set. The settings should be made so as to achieve the following relationship between these two registers: TGRA_3 set value = TCDR set value + TDDR set value The TGRA_3 and TCDR settings are made by setting the values in buffer registers TGRC_3 and TCBR. The values set in TGRC_3 and TCBR are transferred simultaneously to TGRA_3 and TCDR in accordance with the transfer timing selected with bits MD3-MD0 in the timer mode register (TMDR). The updated PWM cycle is reflected from the next cycle when the data update is performed at the crest, and from the current cycle when performed in the trough. Figure 10.36 illustrates the operation when the PWM cycle is updated at the crest. See the following section, Register data updating, for the method of updating the data in each buffer register. Counter value TGRC_3 update TGRA_3 update TCNT_3 TGRA_3 TCNT_4 Time Figure 10.36 Example of PWM Cycle Updating Rev. 4.00 Dec 05, 2005 page 217 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Register Data Updating: In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five PWM duty and carrier cycle registers that have buffer registers and can be updated during operation. There is a temporary register between each of these registers and its buffer register. When subcounter TCNTS is not counting, if buffer register data is updated, the temporary register value is also rewritten. Transfer is not performed from buffer registers to temporary registers when TCNTS is counting; in this case, the value written to a buffer register is transferred after TCNTS halts. The temporary register value is transferred to the compare register at the data update timing set with bits MD3-MD0 in the timer mode register (TMDR). Figure 10.37 shows an example of data updating in complementary PWM mode. This example shows the mode in which data updating is performed at both the counter crest and trough. When rewriting buffer register data, a write to TGRD_4 must be performed at the end of the update. Data transfer from the buffer registers to the temporary registers is performed simultaneously for all five registers after the write to TGRD_4. A write to TGRD_4 must be performed after writing data to the registers to be updated, even when not updating all five registers, or when updating the TGRD_4 data. In this case, the data written to TGRD_4 should be the same as the data prior to the write operation. Rev. 4.00 Dec 05, 2005 page 218 of 564 REJ09B0270-0400 Data update timing: counter crest and trough Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register Transfer from temporary register to compare register : Compare register : Buffer register Transfer from temporary register to compare register Transfer from temporary register to compare register Counter value TGRA_3 TGRC_4 TGRA_4 H'0000 Time BR data2 data2 data3 data1 data2 data3 data4 data4 data3 data5 data5 data4 data6 data6 data6 Temp_R data1 Figure 10.37 Example of Data Update in Complementary PWM Mode Section 10 Multi-Function Timer Pulse Unit (MTU) Rev. 4.00 Dec 05, 2005 page 219 of 564 REJ09B0270-0400 GR data1 Section 10 Multi-Function Timer Pulse Unit (MTU) Initial Output in Complementary PWM Mode: In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in the timer output control register (TOCR). This initial output is the PWM pulse non-active level, and is output from when complementary PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in the dead time register (TDDR). Figure 10.38 shows an example of the initial output in complementary PWM mode. An example of the waveform when the initial PWM duty value is smaller than the TDDR value is shown in Figure 10.39. Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT3, 4 value TCNT_3 TCNT_4 TGR4_A TDDR Time Initial output Positive phase output Negative phase output Dead time Active level Active level Complementary PWM mode (TMDR setting) TCNT3, 4 count start (TSTR setting) Figure 10.38 Example of Initial Output in Complementary PWM Mode (1) Rev. 4.00 Dec 05, 2005 page 220 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3, 4 value TCNT_3 TCNT_4 TDDR TGR_4 Time Initial output Positive phase output Negative phase output Active level Complementary PWM mode (TMDR setting) TCNT_3, 4 count start (TSTR setting) Figure 10.39 Example of Initial Output in Complementary PWM Mode (2) Complementary PWM Mode PWM Output Generation Method: In complementary PWM mode, 3-phase output is performed of PWM waveforms with a non-overlap time between the positive and negative phases. This non-overlap time is called the dead time. A PWM waveform is generated by output of the output level selected in the timer output control register in the event of a compare-match between a counter and data register. While TCNTS is counting, data register and temporary register values are simultaneously compared to create consecutive PWM pulses from 0 to 100%. The relative timing of on and off compare-match occurrence may vary, but the compare-match that turns off each phase takes precedence to secure the dead time and ensure that the positive phase and negative phase on times do not overlap. Figures 10.40 to 10.42 show examples of waveform generation in complementary PWM mode. Rev. 4.00 Dec 05, 2005 page 221 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) The positive phase/negative phase off timing is generated by a compare-match with the solid-line counter, and the on timing by a compare-match with the dotted-line counter operating with a delay of the dead time behind the solid-line counter. In the T1 period, compare-match a that turns off the negative phase has the highest priority, and compare-matches occurring prior to a are ignored. In the T2 period, compare-match c that turns off the positive phase has the highest priority, and compare-matches occurring prior to c are ignored. In normal cases, compare-matches occur in the order a b c d (or c d a' b'), as shown in Figure 10.40. If compare-matches deviate from the a b c d order, since the time for which the negative phase is off is less than twice the dead time, the figure shows the positive phase is not being turned on. If compare-matches deviate from the c d a' b' order, since the time for which the positive phase is off is less than twice the dead time, the figure shows the negative phase is not being turned on. If compare-match c occurs first following compare-match a, as shown in Figure 10.41, comparematch b is ignored, and the negative phase is turned off by compare-match d. This is because turning off of the positive phase has priority due to the occurrence of compare-match c (positive phase off timing) before compare-match b (positive phase on timing) (consequently, the waveform does not change since the positive phase goes from off to off). Similarly, in the example in Figure 10.42, compare-match a' with the new data in the temporary register occurs before compare-match c, but other compare-matches occurring up to c, which turns off the positive phase, are ignored. As a result, the positive phase is not turned on. Thus, in complementary PWM mode, compare-matches at turn-off timings take precedence, and turn-on timing compare-matches that occur before a turn-off timing compare-match are ignored. Rev. 4.00 Dec 05, 2005 page 222 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) T1 period TGR3A_3 c TCDR d T2 period T1 period a b a' b' TDDR H'0000 Positive phase Negative phase Figure 10.40 Example of Complementary PWM Mode Waveform Output (1) T2 period T1 period T1 period TGRA_3 c TCDR a b d a b TDDR H'0000 Positive phase Negative phase Figure 10.41 Example of Complementary PWM Mode Waveform Output (2) Rev. 4.00 Dec 05, 2005 page 223 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) T1 period TGRA_3 T2 period T1 period TCDR a b TDDR c a' H'0000 Positive phase b' d Negative phase Figure 10.42 Example of Complementary PWM Mode Waveform Output (3) T1 period TGRA_3 c d T2 period T1 period TCDR a b a' TDDR b' H'0000 Positive phase Negative phase Figure 10.43 Example of Complementary PWM Mode 0% and 100% Waveform Output (1) Rev. 4.00 Dec 05, 2005 page 224 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) T1 period TGRA_3 T2 period T1 period TCDR a b a TDDR b H'0000 Positive phase c d Negative phase Figure 10.44 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) T1 period TGRA_3 c d T2 period T1 period TCDR a b TDDR H'0000 Positive phase Negative phase Figure 10.45 Example of Complementary PWM Mode 0% and 100% Waveform Output (3) Rev. 4.00 Dec 05, 2005 page 225 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) T1 period T2 period T1 period TGRA_3 TCDR a b TDDR H'0000 Positive phase Negative phase c b' d a' Figure 10.46 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) T1 period TGRA_3 c ad b T2 period T1 period TCDR TDDR H'0000 Positive phase Negative phase Figure 10.47 Example of Complementary PWM Mode 0% and 100% Waveform Output (5) Rev. 4.00 Dec 05, 2005 page 226 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Complementary PWM Mode 0% and 100% Duty Output: In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures 10.43 to 10.47 show output examples. 100% duty output is performed when the data register value is set to H'0000. The waveform in this case has a positive phase with a 100% on-state. 0% duty output is performed when the data register value is set to the same value as TGRA_3. The waveform in this case has a positive phase with a 100% off-state. On and off compare-matches occur simultaneously, but if a turn-on compare-match and turn-off compare-match for the same phase occur simultaneously, both compare-matches are ignored and the waveform does not change. Toggle Output Synchronized with PWM Cycle: In complementary PWM mode, toggle output can be performed in synchronization with the PWM carrier cycle by setting the PSYE bit to 1 in the timer output control register (TOCR). An example of a toggle output waveform is shown in Figure 10.48. This output is toggled by a compare-match between TCNT_3 and TGRA_3 and a compare-match between TCNT4 and H'0000. The output pin for this toggle output is the TIOC3A pin. The initial output is 1. TGRA_3 TCNT_3 TCNT_4 H'0000 Toggle output TIOC3A pin Figure 10.48 Example of Toggle Output Waveform Synchronized with PWM Output Rev. 4.00 Dec 05, 2005 page 227 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Counter Clearing by another Channel: In complementary PWM mode, by setting a mode for synchronization with another channel by means of the timer synchro register (TSYR), and selecting synchronous clearing with bits CCLR2-CCLR0 in the timer control register (TCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by another channel. Figure 10.49 illustrates the operation. Use of this function enables counter clearing and restarting to be performed by means of an external signal. TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Channel 1 Input capture A TCNTS TCNT_1 Synchronous counter clearing by channel 1 input capture A Figure 10.49 Counter Clearing Synchronized with Another Channel Rev. 4.00 Dec 05, 2005 page 228 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output: In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR). Figures 10.50 to 10.53 show examples of brushless DC motor drive waveforms created using TGCR. When output phase switching for a 3-phase brushless DC motor is performed by means of external signals detected with a Hall element, etc., clear the FB bit in TGCR to 0. In this case, the external signals indicating the polarity position are input to channel 0 timer input pins TIOC0A, TIOC0B, and TIOC0C (set with PFC). When an edge is detected at pin TIOC0A, TIOC0B, or TIOC0C, the output on/off state is switched automatically. When the FB bit is 1, the output on/off state is switched when the UF, VF, or WF bit in TGCR is cleared to 0 or set to 1. The drive waveforms are output from the complementary PWM mode 6-phase output pins. With this 6-phase output, in the case of on output, it is possible to use complementary PWM mode output and perform chopping output by setting the N bit or P bit to 1. When the N bit or P bit is 0, level output is selected. The 6-phase output active level (on output level) can be set with the OLSN and OLSP bits in the timer output control register (TOCR) regardless of the setting of the N and P bits. Rev. 4.00 Dec 05, 2005 page 229 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 0, FB = 0, output active level = high Figure 10.50 Example of Output Phase Switching by External Input (1) External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 0, output active level = high Figure 10.51 Example of Output Phase Switching by External Input (2) Rev. 4.00 Dec 05, 2005 page 230 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 0, P = 0, FB = 1, output active level = high Figure 10.52 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (1) TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 1, output active level = high Figure 10.53 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) Rev. 4.00 Dec 05, 2005 page 231 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) A/D Conversion Start Request Setting: In complementary PWM mode, an A/D conversion start request can be set using a TGRA_3 compare-match or a compare-match on a channel other than channels 3 and 4. When start requests using a TGRA_3 compare-match are set, A/D conversion can be started at the center of the PWM pulse. A/D conversion start requests can be set by setting the TTGE bit to 1 in the timer interrupt enable register (TIER). Complementary PWM Mode Output Protection Function Complementary PWM mode output has the following protection functions. * Register and counter miswrite prevention function With the exception of the buffer registers, which can be rewritten at any time, access by the CPU can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary PWM mode by means of bit 13 in the bus controller's bus control register 1 (BCR1). Some registers in channels 3 and 4 concerned are listed below: total 21 registers of TCR_3 and TCR_4; TMDR_3 and TMDR_4; TIORH_3 and TIORH_4; TIORL_3 and TIORL_4; TIER_3 and TIER_4; TCNT_3 and TCNT_4; TGRA_3 and TGRA_4; TGRB_3 and TGRB_4; TOER; TOCR; TGCR; TCDR; and TDDR. This function enables the CPU to prevent miswriting due to the CPU runaway by disabling CPU access to the mode registers, control register, and counters. In access disabled state, an undefined value is read from the registers concerned, and cannot be modified. * Halting of PWM output by external signal The 6-phase PWM output pins can be set automatically to the high-impedance state by inputting specified external signals. There are four external signal input pins. See section 10.9, Port Output Enable (POE), for details. * Halting of PWM output when oscillator is stopped If it is detected that the clock input to this LSI has stopped, the 6-phase PWM output pins automatically go to the high-impedance state. The pin states are not guaranteed when the clock is restarted. See section 4.2, Function for Detecting the Oscillator Halt. Rev. 4.00 Dec 05, 2005 page 232 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.5 10.5.1 Interrupts Interrupts and Priorities There are three kinds of MTU interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, however the priority order within a channel is fixed. For details, see section 6, Interrupt Controller (INTC). Table 10.42 lists the TPU interrupt sources. Rev. 4.00 Dec 05, 2005 page 233 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Table 10.42 MTU Interrupts Channel 0 Name TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U 3 TGI3A TGI3B TGI3C TGI3D TCI3V 4 TGI4A TGI4B TGI4C TGI4D TCI4V Interrupt Source TGRA_0 input capture/compare match TGRB_0 input capture/compare match TGRC_0 input capture/compare match TGRD_0 input capture/compare match TCNT_0 overflow TGRA_1 input capture/compare match TGRB_1 input capture/compare match TCNT_1 overflow TCNT_1 underflow TGRA_2 input capture/compare match TGRB_2 input capture/compare match TCNT_2 overflow TCNT_2 underflow TGRA_3 input capture/compare match TGRB_3 input capture/compare match TGRC_3 input capture/compare match TGRD_3 input capture/compare match TCNT_3 overflow TGRA_4 input capture/compare match TGRB_4 input capture/compare match TGRC_4 input capture/compare match TGRD_4 input capture/compare match TCNT_4 overflow/underflow Interrupt Flag TGFA_0 TGFB_0 TGFC_0 TGFD_0 TCFV_0 TGFA_1 TGFB_1 TCFV_1 TCFU_1 TGFA_2 TGFB_2 TCFV_2 TCFU_2 TGFA_3 TGFB_3 TGFC_3 TGFD_3 TCFV_3 TGFA_4 TGFB_4 TGFC_4 TGFD_4 TCFV_4 DTC Activation Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible Possible Possible Possible Possible Not possible Possible Possible Possible Possible Possible Low Priority High Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The MTU has 16 input capture/compare match interrupts, four each for channels 0, 3, and 4, and two each for channels 1 and 2. Rev. 4.00 Dec 05, 2005 page 234 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The MTU has five overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The MTU has four underflow interrupts, one each for channels 1 and 2. 10.5.2 DTC Activation The DTC can be activated by the TGR input capture/compare match interrupt in each channel. For details, see section 8, Data Transfer Controller (DTC). A total of 17 MTU input capture/compare match interrupts can be used as DTC activation sources, four each for channels 0 and 3, and two each for channels 1 and 2, and five for channel 4. 10.5.3 A/D Converter Activation The A/D converter can be activated by the TGRA input capture/compare match in each channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the MTU conversion start trigger has been selected on the A/D converter at this time, A/D conversion starts. In the MTU, a total of five TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. Rev. 4.00 Dec 05, 2005 page 235 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.6 10.6.1 Operation Timing Input/Output Timing TCNT Count Timing: Figure 10.54 shows TCNT count timing in internal clock operation, and Figure 10.55 shows TCNT count timing in external clock operation (normal mode), and Figure 10.56 shows TCNT count timing in external clock operation (phase counting mode). P Falling edge Rising edge Internal clock TCNT input clock TCNT N-1 N N+1 N+2 Figure 10.54 Count Timing in Internal Clock Operation P Falling edge Rising edge Falling edge External clock TCNT input clock TCNT N-1 N N+1 N+2 Figure 10.55 Count Timing in External Clock Operation Rev. 4.00 Dec 05, 2005 page 236 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) P External clock TCNT input clock Falling edge Rising edge Falling edge TCNT N-1 N N+1 Figure 10.56 Count Timing in External Clock Operation (Phase Counting Mode) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 10.57 shows output compare output timing (normal mode and PWM mode) and Figure 10.58 shows output compare output timing (complementary PWM mode and reset synchronous PWM mode). P TCNT input clock N N+1 TCNT TGR Compare match signal TIOC pin N Figure 10.57 Output Compare Output Timing (Normal Mode/PWM Mode) Rev. 4.00 Dec 05, 2005 page 237 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) P TCNT input clock TCNT N N+1 TGR N Compare match signal TIOC pin Figure 10.58 Output Compare Output Timing (Complementary PWM Mode/Reset Synchronous PWM Mode) Input Capture Signal Timing: Figure 10.59 shows input capture signal timing. P Input capture input Input capture signal TCNT N N+1 N+2 TGR N N+2 Figure 10.59 Input Capture Input Signal Timing Rev. 4.00 Dec 05, 2005 page 238 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Timing for Counter Clearing by Compare Match/Input Capture: Figure 10.60 shows the timing when counter clearing on compare match is specified, and Figure 10.61 shows the timing when counter clearing on input capture is specified. P Compare match signal Counter clear signal TCNT N H'0000 TGR N Figure 10.60 Counter Clear Timing (Compare Match) P Input capture signal Counter clear signal TCNT N H'0000 TGR N Figure 10.61 Counter Clear Timing (Input Capture) Rev. 4.00 Dec 05, 2005 page 239 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Buffer Operation Timing: Figures 10.62 and 10.63 show the timing in buffer operation. P TCNT Compare match signal TGRA, TGRB TGRC, TGRD n n+1 n N N Figure 10.62 Buffer Operation Timing (Compare Match) P Input capture signal TCNT TGRA, TGRB TGRC, TGRD N N+1 n N N+1 n N Figure 10.63 Buffer Operation Timing (Input Capture) Rev. 4.00 Dec 05, 2005 page 240 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 10.64 shows the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. P TCNT input clock TCNT N N+1 TGR Compare match signal TGF flag N TGI interrupt Figure 10.64 TGI Interrupt Timing (Compare Match) Rev. 4.00 Dec 05, 2005 page 241 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) TGF Flag Setting Timing in Case of Input Capture: Figure 10.65 shows the timing for setting of the TGF flag in TSR on input capture, and TGI interrupt request signal timing. P Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 10.65 TGI Interrupt Timing (Input Capture) Rev. 4.00 Dec 05, 2005 page 242 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) TCFV Flag/TCFU Flag Setting Timing: Figure 10.66 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 10.67 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing. P TCNT input clock TCNT (overflow) Overflow signal H'FFFF H'0000 TCFV flag TCIV interrupt Figure 10.66 TCIV Interrupt Setting Timing P TCNT input clock TCNT (underflow) Underflow signal TCFU flag H'0000 H'FFFF TCIU interrupt Figure 10.67 TCIU Interrupt Setting Timing Rev. 4.00 Dec 05, 2005 page 243 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated, the flag is cleared automatically. Figure 10.68 shows the timing for status flag clearing by the CPU, and Figure 10.69 shows the timing for status flag clearing by the DTC. TSR write cycle T1 T2 P Address TSR address Write signal Status flag Interrupt request signal Figure 10.68 Timing for Status Flag Clearing by the CPU DTC read cycle T1 P Destination address DTC write cycle T1 T2 T2 Address Source address Status flag Interrupt request signal Figure 10.69 Timing for Status Flag Clearing by DTC Activation Rev. 4.00 Dec 05, 2005 page 244 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.7 10.7.1 Usage Notes Module Standby Mode Setting MTU operation can be disabled or enabled using the module standby register. The initial setting is for MTU operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 21, Power-Down Modes. 10.7.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower pulse widths. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10.70 shows the input clock conditions in phase counting mode. Phase Phase differdifference Overlap ence Overlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more Pulse width : 2.5 states or more Figure 10.70 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Rev. 4.00 Dec 05, 2005 page 245 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.7.3 Caution on Period Setting When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= Where P (N + 1) f : Counter frequency P : Peripheral clock operating frequency N : TGR set value Contention between TCNT Write and Clear Operations 10.7.4 If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10.71 shows the timing in this case. TCNT write cycle T1 T2 P Address Write signal Counter clear signal TCNT TCNT address N H'0000 Figure 10.71 Contention between TCNT Write and Clear Operations Rev. 4.00 Dec 05, 2005 page 246 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.7.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 10.72 shows the timing in this case. TCNT write cycle T1 T2 P Address TCNT address Write signal TCNT input clock TCNT N TCNT write data M Figure 10.72 Contention between TCNT Write and Increment Operations Rev. 4.00 Dec 05, 2005 page 247 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.7.6 Contention between TGR Write and Compare Match When a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the compare match signal is generated. Figure 10.73 shows the timing in this case. TGR write cycle T1 T2 P Address Write signal Compare match signal TCNT TGR N N TGR write data N+1 M TGR address Figure 10.73 Contention between TGR Write and Compare Match Rev. 4.00 Dec 05, 2005 page 248 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.7.7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation differs depending on channel 0 and channels 3 and 4: data on channel 0 is that after write, and on channels 3 and 4, before write. Figures 10.74 and 10.75 show the timing in this case. TGR write cycle T1 T2 P Address Write signal Compare match signal Compare match buffer signal Buffer register TGR N M M Buffer register address Buffer register write data Figure 10.74 Contention between Buffer Register Write and Compare Match (Channel 0) Rev. 4.00 Dec 05, 2005 page 249 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) TGR write cycle T1 T2 P Address Buffer register address Write signal Compare match signal Compare match buffer signal Buffer register write data Buffer register N M TGR N Figure 10.75 Contention between Buffer Register Write and Compare Match (Channels 3 and 4) Rev. 4.00 Dec 05, 2005 page 250 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.7.8 Contention between TGR Read and Input Capture If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be that in the buffer after input capture transfer. Figure 10.76 shows the timing in this case. TGR read cycle T1 T2 P Address TGR address Read signal Input capture signal TGR X M Internal data bus M Figure 10.76 Contention between TGR Read and Input Capture Rev. 4.00 Dec 05, 2005 page 251 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.7.9 Contention between TGR Write and Input Capture If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10.77 shows the timing in this case. TGR write cycle T1 T2 P Address Write signal Input capture signal TCNT TGR M M TGR address Figure 10.77 Contention between TGR Write and Input Capture Rev. 4.00 Dec 05, 2005 page 252 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.7.10 Contention between Buffer Register Write and Input Capture If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10.78 shows the timing in this case. Buffer register write cycle T1 T2 P Address Write signal Input capture signal TCNT TGR Buffer register M N N M Buffer register address Figure 10.78 Contention between Buffer Register Write and Input Capture 10.7.11 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection With timer counters TCNT1 and TCNT2 in a cascade connection, when a contention occurs during TCNT_1 count (during a TCNT_2 overflow/underflow) in the T2 state of the TCNT_2 write cycle, the write to TCNT_2 is conducted, and the TCNT_1 count signal is disabled. At this point, if there is match with TGRA_1 and the TCNT_1 value, a compare signal is issued. Furthermore, when the TCNT_1 count clock is selected as the input capture source of channel 0, TGRA_0 to D_0 carry out the input capture operation. In addition, when the compare match/input capture is selected as the input capture source of TGRB_1, TGRB_1 carries out input capture operation. The timing is shown in Figure 10.79. For cascade connections, be sure to synchronize settings for channels 1 and 2 when setting TCNT clearing. Rev. 4.00 Dec 05, 2005 page 253 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) TCNT write cycle T1 P Address Write signal TCNT_2 H'FFFE H'FFFF TCNT_2 write data TGR2A_2 to TGR2B_2 Ch2 comparematch signal A/B TCNT_1 input clock TCNT_1 TGRA_1 Ch1 comparematch signal A TGRB_1 Ch1 input capture signal B TCNT_0 TGRA_0 to TGRD_0 Ch0 input capture signal A to D P N M M M Disabled H'FFFF N N+1 T1 TCNT_2 address Q P Figure 10.79 TCNT_2 Write and Overflow/Underflow Contention with Cascade Connection Rev. 4.00 Dec 05, 2005 page 254 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.7.12 Counter Value during Complementary PWM Mode Stop When counting operation is stopped with TCNT_3 and TCNT_4 in complementary PWM mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is set to H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state. This explanatory diagram is shown in Figure 10.80. When counting begins in another operating mode, be sure that TCNT_3 and TCNT_4 are set to the initial values. TGRA_3 TCDR TCNT_3 TCNT_4 TDDR H'0000 Complementary PWM mode operation Counter operation stop Complementary PWM mode operation Complementary PMW restart Figure 10.80 Counter Value during Complementary PWM Mode Stop 10.7.13 Buffer Operation Setting in Complementary PWM Mode In complementary PWM mode, conduct rewrites by buffer operation for the PWM cycle setting register (TGRA_3), timer cycle data register (TCDR), and duty setting registers (TGRB_3, TRGA_4, and TGRB_4). In complementary PWM mode, channel 3 and channel 4 buffers operate in accordance with bit settings BFA and BFB of TMDR_3. When TMDR_3's BFA bit is set to 1, TGRC_3 functions as a buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TRGA_4, while the TCBR functions as the TCDR's buffer register. Rev. 4.00 Dec 05, 2005 page 255 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.7.14 Reset Sync PWM Mode Buffer Operation and Compare Match Flag When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits of TMDR_4 to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit of TMDR_4 is set to 1. In reset sync PWM mode, the channel 3 and channel 4 buffers operate in accordance with the BFA and BFB bit settings of TMDR_3. For example, if the BFA bit of TMDR_3 is set to 1, TGRC_3 functions as the buffer register for TGRA_3. At the same time, TGRC_4 functions as the buffer register for TRGA_4. The TGFC bit and TGFD bit of TSR_3 and TSR_4 are not set when TGRC_3 and TGRD_3 are operating as buffer registers. Figure 10.81 shows an example of operations for TGR_3, TGR_4, TIOC3, and TIOC4, with TMDR_3's BFA and BFB bits set to 1, and TMDR_4's BFA and BFB bits set to 0. TGRA_3 TCNT3 Point a Buffer transfer with compare match A3 TGRA_3, TGRC_3 TGRC_3 TGRB_3, TGRA_4, TGRB_4 Point b TGRD_3, TGRC_4, TGRD_4 H'0000 TGRB_3, TGRD_3, TGRA_4, TGRC_4, TGRB_4, TGRD_4 TIOC3A TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D TGFC TGFD Not set Not set Figure 10.81 Buffer Operation and Compare-Match Flags in Reset Sync PWM Mode Rev. 4.00 Dec 05, 2005 page 256 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.7.15 Overflow Flags in Reset Sync PWM Mode When set to reset sync PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit of TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the TCR_3 setting. In reset sync PWM mode, with cycle register TGRA_3's set value at H'FFFF, when specifying TGR3A compare-match for the counter clear source, TCNT_3 and TCNT_4 count up to H'FFFF, then a compare-match occurs with TGRA_3, and TCNT_3 and TCNT_4 are both cleared. At this point, TSR's overflow flag TCFV bit is not set. Figure 10.82 shows a TCFV bit operation example in reset sync PWM mode with a set value for cycle register TGRA_3 of H'FFFF, when a TGRA_3 compare-match has been specified without synchronous setting for the counter clear source. Counter cleared by compare match 3A TGRA_3 (H'FFFF) TCNT_3 = TCNT_4 H'0000 TCFV_3 TCFV_4 Not set Not set Figure 10.82 Reset Sync PWM Mode Overflow Flag Rev. 4.00 Dec 05, 2005 page 257 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.7.16 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10.83 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR. P TCNT input clock TCNT Counter clear signal TGF Disabled H'FFFF H'0000 TCFV Figure 10.83 Contention between Overflow and Counter Clearing Rev. 4.00 Dec 05, 2005 page 258 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.7.17 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10.84 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T1 T2 P Address Write signal TCNT address TCNT write data TCNT H'FFFF M TCFV flag Figure 10.84 Contention between TCNT Write and Overflow 10.7.18 Cautions on Transition from Normal Operation or PWM Mode 1 to ResetSynchronous PWM Mode When making a transition from channel 3 or 4 normal operation or PWM mode 1 to resetsynchronous PWM mode, if the counter is halted with the output pins (TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, TIOC4D) in the high-impedance state, followed by the transition to reset-synchronous PWM mode and operation in that mode, the initial pin output will not be correct. When making a transition from normal operation to reset-synchronous PWM mode, write H'11 to registers TIORH_3, TIORL_3, TIORH_4, and TIORL_4 to initialize the output pins to low level output, then set an initial register value of H'00 before making the mode transition. When making a transition from PWM mode 1 to reset-synchronous PWM mode, first switch to normal operation, then initialize the output pins to low level output and set an initial register value of H'00 before making the transition to reset-synchronous PWM mode. Rev. 4.00 Dec 05, 2005 page 259 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.7.19 Output Level in Complementary PWM Mode and Reset-Synchronous PWM Mode When channels 3 and 4 are in complementary PWM mode or reset-synchronous PWM mode, the PWM waveform output level is set with the OLSP and OLSN bits in the timer output control register (TOCR). In the case of complementary PWM mode or reset-synchronous PWM mode, TIOR should be set to H'00. 10.7.20 Interrupts in Module Standby Mode If module standby mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering module standby mode. 10.7.21 Simultaneous Input Capture of TCNT_1 and TCNT_2 in Cascade Connection When cascade-connected timer counters (TCNT_1 and TCNT_2) are operated, cascade values cannot be captured even if input capture is executed simultaneously with TIOC1A or TIOC1B and TIOC2A or TIOC2B. 10.7.22 Notes on Buffer Operation Settings When enabling buffer operation, clear to 0 bit TGIEC or TGIED in the timer interrupt enable register (TIER) corresponding to the TGRC or TGRD register used as the buffer register. Rev. 4.00 Dec 05, 2005 page 260 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.8 10.8.1 MTU Output Pin Initialization Operating Modes The MTU has the following six operating modes. Waveform output is possible in all of these modes. * Normal mode (channels 0 to 4) * PWM mode 1 (channels 0 to 4) * PWM mode 2 (channels 0 to 2) * Phase counting modes 1-4 (channels 1 and 2) * Complementary PWM mode (channels 3 and 4) * Reset-synchronous PWM mode (channels 3 and 4) The MTU output pin initialization method for each of these modes is described in this section. 10.8.2 Reset Start Operation The MTU output pins (TIOC*) are initialized low by a reset or in standby mode. Since MTU pin function selection is performed by the pin function controller (PFC), when the PFC is set, the MTU pin states at that point are output to the ports. When MTU output is selected by the PFC immediately after a reset, the MTU output initial level, low, is output directly at the port. When the active level is low, the system will operate at this point, and therefore the PFC setting should be made after initialization of the MTU output pins is completed. Note: Channel number and port notation are substituted for *. Rev. 4.00 Dec 05, 2005 page 261 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc. If an error occurs during MTU operation, MTU output should be cut by the system. Cutoff is performed by switching the pin output to port output with the PFC and outputting the inverse of the active level. For large-current pins, output can also be cut by hardware, using port output enable (POE). The pin initialization procedures for re-setting due to an error during operation, etc., and the procedures for restarting in a different mode after re-setting, are shown below. The MTU has six operating modes, as stated above. There are thus 36 mode transition combinations, but some transitions are not available with certain channel and mode combinations. Possible mode transition combinations are shown in table 10.43. Table 10.43 Mode Transition Combinations After Before Normal PWM1 PWM2 PCM CPWM RPWM Normal (1) (7) (13) (17) (21) (26) PWM1 (2) (8) (14) (18) (22) (27) PWM2 (3) (9) (15) (19) None None PCM (4) (10) (16) (20) None None CPWM (5) (11) None None (23) (24) (28) RPWM (6) (12) None None (25) (29) Legend: Normal: Normal mode PWM1: PWM mode 1 PWM2: PWM mode 2 PCM: Phase counting modes 1-4 CPWM: Complementary PWM mode RPWM: Reset-synchronous PWM mode The above abbreviations are used in some places in following descriptions. Rev. 4.00 Dec 05, 2005 page 262 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, Etc. * When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting. * In PWM mode 1, since a waveform is not output to the TIOC*B (TIOC *D) pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 1. * In PWM mode 2, since a waveform is not output to the cycle register pin, setting TIOR will not initialize the pins. If initialization is required, carry it out in normal mode, then switch to PWM mode 2. * In normal mode or PWM mode 2, if TGRC and TGRD operate as buffer registers, setting TIOR will not initialize the buffer register pins. If initialization is required, clear buffer mode, carry out initialization, then set buffer mode again. * In PWM mode 1, if either TGRC or TGRD operates as a buffer register, setting TIOR will not initialize the TGRC pin. To initialize the TGRC pin, clear buffer mode, carry out initialization, then set buffer mode again. * When making a transition to a mode (CPWM, RPWM) in which the pin output level is selected by the timer output control register (TOCR) setting, switch to normal mode and perform initialization with TIOR, then restore TIOR to its initial value, and temporarily disable channel 3 and 4 output with the timer output master enable register (TOER). Then operate the unit in accordance with the mode setting procedure (TOCR setting, TMDR setting, TOER setting). Pin initialization procedures are described below for the numbered combinations in table 10.43. The active level is assumed to be low. Note: Channel number is substituted for * indicated in this article. Rev. 4.00 Dec 05, 2005 page 263 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (1) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode: Figure 10.85 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 High-Z High-Z Figure 10.85 Error Occurrence in Normal Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. After a reset, MTU output is low and ports are in the high-impedance state. After a reset, the TMDR setting is for normal mode. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. 11. Not necessary when restarting in normal mode. 12. Initialize the pins with TIOR. 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 264 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 10.86 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 High-Z High-Z * Not initialized (TIOC*B) Figure 10.86 Error Occurrence in Normal Mode, Recovery in PWM Mode 1 1 to 10 are the same as in Figure 10.85. 11. Set PWM mode 1. 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 1.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 265 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (3) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 10.87 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting. 1 2 3 RESET TMDR TOER (normal) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 High-Z High-Z * Not initialized (cycle register) Figure 10.87 Error Occurrence in Normal Mode, Recovery in PWM Mode 2 1 to 10 are the same as in Figure 10.85. 11. Set PWM mode 2. 12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized. If initialization is required, initialize in normal mode, then switch to PWM mode 2.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0-2, and therefore TOER setting is not necessary. Rev. 4.00 Dec 05, 2005 page 266 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (4) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 10.88 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after resetting. 1 2 3 RESET TMDR TOER (normal) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PCM) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 High-Z High-Z Figure 10.88 Error Occurrence in Normal Mode, Recovery in Phase Counting Mode 1 to 10 are the same as in Figure 10.85. 11. Set phase counting mode. 12. Initialize the pins with TIOR. 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary. Rev. 4.00 Dec 05, 2005 page 267 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (5) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 10.89 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in complementary PWM mode after re-setting. 1 2 3 4 RESET TMDR TOER TIOR (normal) (1) (1 init 0 out) 5 6 PFC TSTR (MTU) (1) 7 Match 8 9 10 Error PFC TSTR occurs (PORT) (0) 13 14 11 12 15 (16) (17) (18) TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (0 init (disabled) (0) (CPWM) (1) (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 10.89 Error Occurrence in Normal Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in Figure 10.85. 11. Initialize the normal mode waveform generation section with TIOR. 12. Disable operation of the normal mode waveform generation section with TIOR. 13. Disable channel 3 and 4 output with TOER. 14. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 15. Set complementary PWM. 16. Enable channel 3 and 4 output with TOER. 17. Set MTU output with the PFC. 18. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 268 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (6) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode: Figure 10.90 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronous PWM mode after re-setting. 1 2 3 4 RESET TMDR TOER TIOR (normal) (1) (1 init 0 out) 5 6 PFC TSTR (MTU) (1) 7 Match 8 9 10 Error PFC TSTR occurs (PORT) (0) 13 14 11 12 15 16 17 18 TIOR TIOR TOER TOCR TMDR TOER PFC TSTR (0 init (disabled) (0) (CPWM) (1) (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 10.90 Error Occurrence in Normal Mode, Recovery in Reset-Synchronous PWM Mode 1 to 13 are the same as in Figure 10.89. 14. Select the reset-synchronous PWM output level and cyclic output enabling/disabling with TOCR. 15. Set reset-synchronous PWM. 16. Enable channel 3 and 4 output with TOER. 17. Set MTU output with the PFC. 18. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 269 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (7) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode: Figure 10.91 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 High-Z High-Z * Not initialized (TIOC*B) Figure 10.91 Error Occurrence in PWM Mode 1, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. After a reset, MTU output is low and ports are in the high-impedance state. Set PWM mode 1. For channels 3 and 4, enable output with TOER before initializing the pins with TIOR. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 1, the TIOC*B side is not initialized.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. 11. Set normal mode. 12. Initialize the pins with TIOR. 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 270 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (8) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1: Figure 10.92 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 High-Z High-Z * Not initialized (TIOC*B) * Not initialized (TIOC*B) Figure 10.92 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 1 1 to 10 are the same as in Figure 10.91. 11. Not necessary when restarting in PWM mode 1. 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 271 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (9) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2: Figure 10.93 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting. 1 2 3 RESET TMDR TOER (PWM1) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 High-Z High-Z * Not initialized (cycle register) * Not initialized (TIOC*B) Figure 10.93 Error Occurrence in PWM Mode 1, Recovery in PWM Mode 2 1 to 10 are the same as in Figure 10.91. 11. Set PWM mode 2. 12. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Note: PWM mode 2 can only be set for channels 0-2, and therefore TOER setting is not necessary. Rev. 4.00 Dec 05, 2005 page 272 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (10) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode: Figure 10.94 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after resetting. 1 2 3 RESET TMDR TOER (PWM1) (1) 4 5 6 TIOR PFC TSTR (1 init (MTU) (1) 0 out) 7 Match 8 9 10 11 Error PFC TSTR TMDR occurs (PORT) (0) (PCM) 12 13 14 TIOR PFC TSTR (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 High-Z High-Z * Not initialized (TIOC*B) Figure 10.94 Error Occurrence in PWM Mode 1, Recovery in Phase Counting Mode 1 to 10 are the same as in Figure 10.91. 11. Set phase counting mode. 12. Initialize the pins with TIOR. 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Note: Phase counting mode can only be set for channels 1 and 2, and therefore TOER setting is not necessary. Rev. 4.00 Dec 05, 2005 page 273 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (11) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Complementary PWM Mode: Figure 10.95 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re-setting. 1 2 3 4 RESET TMDR TOER TIOR (PWM1) (1) (1 init 0 out) 5 6 PFC TSTR (MTU) (1) 7 Match 14 8 9 10 11 12 13 15 16 17 18 19 Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (normal) (0 init (disabled) (0) (CPWM) (1) (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 * Not initialized (TIOC3B) * Not initialized (TIOC3D) High-Z High-Z High-Z Figure 10.95 Error Occurrence in PWM Mode 1, Recovery in Complementary PWM Mode 1 to 10 are the same as in Figure 10.91. 11. Set normal mode for initialization of the normal mode waveform generation section. 12. Initialize the PWM mode 1 waveform generation section with TIOR. 13. Disable operation of the PWM mode 1 waveform generation section with TIOR. 14. Disable channel 3 and 4 output with TOER. 15. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 16. Set complementary PWM. 17. Enable channel 3 and 4 output with TOER. 18. Set MTU output with the PFC. 19. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 274 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (12) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Reset-Synchronous PWM Mode: Figure 10.96 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in reset-synchronous PWM mode after re-setting. 1 2 3 4 RESET TMDR TOER TIOR (PWM1) (1) (1 init 0 out) 5 6 PFC TSTR (MTU) (1) 7 Match 14 8 9 10 11 12 13 15 16 17 18 19 Error PFC TSTR TMDR TIOR TIOR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (normal) (0 init (disabled) (0) (RPWM) (1) (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 * Not initialized (TIOC3B) * Not initialized (TIOC3D) High-Z High-Z High-Z Figure 10.96 Error Occurrence in PWM Mode 1, Recovery in Reset-Synchronous PWM Mode 1 to 14 are the same as in Figure 10.95. 15. Select the reset-synchronous PWM output level and cyclic output enabling/disabling with TOCR. 16. Set reset-synchronous PWM. 17. Enable channel 3 and 4 output with TOER. 18. Set MTU output with the PFC. 19. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 275 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (13) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode: Figure 10.97 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting. 1 2 3 RESET TMDR TIOR (PWM2) (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 * Not initialized (cycle register) High-Z High-Z Figure 10.97 Error Occurrence in PWM Mode 2, Recovery in Normal Mode 1. 2. 3. After a reset, MTU output is low and ports are in the high-impedance state. Set PWM mode 2. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the example, TIOC *A is the cycle register.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. 4. 5. 6. 7. 8. 9. 10. Set normal mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 276 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (14) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1: Figure 10.98 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting. 1 2 3 RESET TMDR TIOR (PWM2) (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 * Not initialized (cycle register) * Not initialized (TIOC*B) High-Z High-Z Figure 10.98 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 1 1 to 9 are the same as in Figure 10.97. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC*B side is not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 277 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (15) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2: Figure 10.99 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting. 1 2 3 4 5 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PWM2) (1 init (MTU) (1) occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 * Not initialized (cycle register) * Not initialized (cycle register) High-Z High-Z Figure 10.99 Error Occurrence in PWM Mode 2, Recovery in PWM Mode 2 1 to 9 are the same as in Figure 10.97. 10. Not necessary when restarting in PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 278 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (16) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Phase Counting Mode: Figure 10.100 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after resetting. 1 2 3 RESET TMDR TIOR (PWM2) (1 init 0 out) 4 5 6 7 8 9 10 PFC TSTR Match Error PFC TSTR TMDR (MTU) (1) occurs (PORT) (0) (PCM) 11 12 13 TIOR PFC TSTR (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 * Not initialized (cycle register) High-Z High-Z Figure 10.100 Error Occurrence in PWM Mode 2, Recovery in Phase Counting Mode 1 to 9 are the same as in Figure 10.97. 10. Set phase counting mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 279 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (17) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Normal Mode: Figure 10.101 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting. 1 2 3 4 5 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PCM) (1 init (MTU) (1) occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 High-Z High-Z Figure 10.101 Error Occurrence in Phase Counting Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. After a reset, MTU output is low and ports are in the high-impedance state. Set phase counting mode. Initialize the pins with TIOR. (The example shows initial high output, with low output on compare-match occurrence.) Set MTU output with the PFC. The count operation is started by TSTR. Output goes low on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. The count operation is stopped by TSTR. 10. Set in normal mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 280 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (18) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 10.102 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 4 5 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PCM) (1 init (MTU) (1) occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 * Not initialized (TIOC*B) High-Z High-Z Figure 10.102 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 1 1 to 9 are the same as in Figure 10.101. 10. Set PWM mode 1. 11. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 281 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (19) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 10.103 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting. 1 2 RESET TMDR (PCM) 3 TIOR (1 init 0 out) 4 5 6 7 8 9 10 11 12 13 PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (MTU) (1) occurs (PORT) (0) (PWM2) (1 init (MTU) (1) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 * Not initialized (cycle register) High-Z High-Z Figure 10.103 Error Occurrence in Phase Counting Mode, Recovery in PWM Mode 2 1 to 9 are the same as in Figure 10.101. 10. Set PWM mode 2. 11. Initialize the pins with TIOR. (In PWM mode 2, the cycle register pins are not initialized.) 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 282 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (20) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 10.104 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting. 1 2 3 4 5 6 7 8 9 10 11 12 13 RESET TMDR TIOR PFC TSTR Match Error PFC TSTR TMDR TIOR PFC TSTR (PCM) (1 init (MTU) (1) occurs (PORT) (0) (PCM) (1 init (MTU) (1) 0 out) 0 out) MTU module output TIOC*A TIOC*B Port output PEn PEn n=0 to 15 High-Z High-Z Figure 10.104 Error Occurrence in Phase Counting Mode, Recovery in Phase Counting Mode 1 to 9 are the same as in Figure 10.101. 10. Not necessary when restarting in phase counting mode. 11. Initialize the pins with TIOR. 12. Set MTU output with the PFC. 13. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 283 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (21) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Normal Mode: Figure 10.105 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 10.105 Error Occurrence in Complementary PWM Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. After a reset, MTU output is low and ports are in the high-impedance state. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. Set complementary PWM. Enable channel 3 and 4 output with TOER. Set MTU output with the PFC. The count operation is started by TSTR. The complementary PWM waveform is output on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. (MTU output becomes the complementary PWM output initial value.) 11. Set normal mode. (MTU output goes low.) 12. Initialize the pins with TIOR. 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 284 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (22) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 10.106 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z * Not initialized (TIOC3B) * Not initialized (TIOC3D) Figure 10.106 Error Occurrence in Complementary PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in Figure 10.105. 11. Set PWM mode 1. (MTU output goes low.) 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 285 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (23) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 10.107 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time the counter was stopped). 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 Error PFC TSTR PFC TSTR Match occurs (PORT) (0) (MTU) (1) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 10.107 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in Figure 10.105. 11. Set MTU output with the PFC. 12. Operation is restarted by TSTR. 13. The complementary PWM waveform is output on compare-match occurrence. Rev. 4.00 Dec 05, 2005 page 286 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (24) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 10.108 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using completely new cycle and duty settings). 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 15 16 17 Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (normal) (0) (CPWM) (1) (MTU) (1) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 10.108 Error Occurrence in Complementary PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in Figure 10.105. 11. Set normal mode and make new settings. (MTU output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the complementary PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set complementary PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU output with the PFC. 17. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 287 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (25) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode: Figure 10.109 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in reset-synchronous PWM mode. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 15 16 17 Error PFC TSTR TMDR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (normal) (0) (RPWM) (1) (MTU) (1) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 10.109 Error Occurrence in Complementary PWM Mode, Recovery in Reset-Synchronous PWM Mode 1 to 10 are the same as in Figure 10.105. 11. Set normal mode. (MTU output goes low.) 12. Disable channel 3 and 4 output with TOER. 13. Select the reset-synchronous PWM mode output level and cyclic output enabling/disabling with TOCR. 14. Set reset-synchronous PWM. 15. Enable channel 3 and 4 output with TOER. 16. Set MTU output with the PFC. 17. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 288 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (26) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Normal Mode: Figure 10.110 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in normal mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (CPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (normal) (1 init (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 10.110 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Normal Mode 1. 2. 3. 4. 5. 6. 7. 8. 9. After a reset, MTU output is low and ports are in the high-impedance state. Select the reset-synchronous PWM output level and cyclic output enabling/disabling with TOCR. Set reset-synchronous PWM. Enable channel 3 and 4 output with TOER. Set MTU output with the PFC. The count operation is started by TSTR. The reset-synchronous PWM waveform is output on compare-match occurrence. An error occurs. Set port output with the PFC and output the inverse of the active level. 10. The count operation is stopped by TSTR. (MTU output becomes the reset-synchronous PWM output initial value.) 11. Set normal mode. (MTU positive phase output is low, and negative phase output is high.) 12. Initialize the pins with TIOR. 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 289 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (27) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 10.111 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in PWM mode 1 after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 Error PFC TSTR TMDR TIOR PFC TSTR occurs (PORT) (0) (PWM1) (1 init (MTU) (1) 0 out) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z * Not initialized (TIOC3B) * Not initialized (TIOC3D) Figure 10.111 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in PWM Mode 1 1 to 10 are the same as in Figure 10.110. 11. Set PWM mode 1. (MTU positive phase output is low, and negative phase output is high.) 12. Initialize the pins with TIOR. (In PWM mode 1, the TIOC *B side is not initialized.) 13. Set MTU output with the PFC. 14. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 290 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (28) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 10.112 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in complementary PWM mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 14 15 16 Error PFC TSTR TOER TOCR TMDR TOER PFC TSTR occurs (PORT) (0) (0) (CPWM) (1) (MTU) (1) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 10.112 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Complementary PWM Mode 1 to 10 are the same as in Figure 10.110. 11. Disable channel 3 and 4 output with TOER. 12. Select the complementary PWM output level and cyclic output enabling/disabling with TOCR. 13. Set complementary PWM. (The MTU cyclic output pin goes low.) 14. Enable channel 3 and 4 output with TOER. 15. Set MTU output with the PFC. 16. Operation is restarted by TSTR. Rev. 4.00 Dec 05, 2005 page 291 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) (29) Operation when Error Occurs during Reset-Synchronous PWM Mode Operation, and Operation is Restarted in Reset-Synchronous PWM Mode: Figure 10.113 shows an explanatory diagram of the case where an error occurs in reset-synchronous PWM mode and operation is restarted in reset-synchronous PWM mode after re-setting. 1 2 3 4 5 6 RESET TOCR TMDR TOER PFC TSTR (RPWM) (1) (MTU) (1) 7 Match 8 9 10 11 12 13 Error PFC TSTR PFC TSTR Match occurs (PORT) (0) (MTU) (1) MTU module output TIOC3A TIOC3B TIOC3D Port output PE8 PE9 PE11 High-Z High-Z High-Z Figure 10.113 Error Occurrence in Reset-Synchronous PWM Mode, Recovery in Reset-Synchronous PWM Mode 1 to 10 are the same as in Figure 10.110. 11. Set MTU output with the PFC. 12. Operation is restarted by TSTR. 13. The reset-synchronous PWM waveform is output on compare-match occurrence. Rev. 4.00 Dec 05, 2005 page 292 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.9 Port Output Enable (POE) The port output enable (POE) can be used to establish a high-impedance state for high-current pins, by changing the POE0-POE3 pin input, depending on the output status of the high-current pins (PE9/TIOC3B, PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C, PE15/TIOC4D/IRQOUT). It can also simultaneously generate interrupt requests. The high-current pins also become high-impedance regardless of whether these pin functions are selected in cases such as when the oscillator stops or in standby mode. 10.9.1 Features * Each of the POE0-POE3 input pins can be set for falling edge, P/8 x 16, P/16 x 16, or P/128 x 16 low-level sampling. * High-current pins can be set to high-impedance state by POE0-POE3 pin falling-edge or lowlevel sampling. * High-current pins can be set to high-impedance state when the high-current pin output levels are compared and simultaneous low-level output continues for one cycle or more. * Interrupts can be generated by input-level sampling or output-level comparison results. Rev. 4.00 Dec 05, 2005 page 293 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) The POE has input-level detection circuitry and output-level detection circuitry, as shown in the block diagram of Figure 10.114. TIOC3B TIOC3D TIOC4A TIOC4C TIOC4B TIOC4D Output level detection circuit Output level detection circuit Output level detection circuit OCSR Highimpedance request control signal Interrupt request (MTUPOE) ICSR1 Input level detection circuit Falling-edge detection circuit Low-level detection circuit POE3 POE2 POE1 POE0 /8 /16 /128 Legend: OCSR: Output level control/status register ICSR1: Input level control/status register Figure 10.114 POE Block Diagram Rev. 4.00 Dec 05, 2005 page 294 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.9.2 Pin Configuration Table 10.44 Pin Configuration Name Port output enable input pins Abbreviation POE0-POE3 I/O Input Description Input request signals to make highcurrent pins high-impedance state Table 10.45 shows output-level comparisons with pin combinations. Table 10.45 Pin Combinations Pin Combination PE9/TIOC3B and PE11/TIOC3D I/O Output Description All high-current pins are made high-impedance state when the pins simultaneously output low-level for longer than 1 cycle. All high-current pins are made high-impedance state when the pins simultaneously output low-level for longer than 1 cycle. All high-current pins are made high-impedance state when the pins simultaneously output low-level for longer than 1 cycle. PE12/TIOC4A and PE14/TIOC4C Output PE13/TIOC4B/MRES and PE15/TIOC4D/IRQOUT Output 10.9.3 Register Configuration The POE has the two registers. The input level control/status register 1 (ICSR1) controls both POE0-POE3 pin input signal detection and interrupts. The output level control/status register (OCSR) controls both the enable/disable of output comparison and interrupts. Input Level Control/Status Register 1 (ICSR1): The input level control/status register (ICSR1) is a 16-bit readable/writable register that selects the POE0 to POE3 pin input modes, controls the enable/disable of interrupts, and indicates status. Rev. 4.00 Dec 05, 2005 page 295 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Initial value 0 Bit 15 Bit Name POE3F R/W R/(W)* Description POE3 Flag This flag indicates that a high impedance request has been input to the POE3 pin Clear condition: * * By writing 0 to POE3F after reading a POE3F = 1 When the input set by ICSR1 bits 7 and 6 occurs at the POE3 pin Set condition: 14 POE2F 0 R/(W)* POE2 Flag This flag indicates that a high impedance request has been input to the POE2 pin Clear condition: * * By writing 0 to POE2F after reading a POE2F = 1 When the input set by ICSR1 bits 5 and 4 occurs at the POE2 pin Set condition: 13 POE1F 0 R/(W)* POE1 Flag This flag indicates that a high impedance request has been input to the POE1 pin Clear condition: * * By writing 0 to POE1F after reading a POE1F = 1 When the input set by ICSR1 bits 3 and 2 occurs at the POE1 pin Set condition: 12 POE0F 0 R/(W)* POE0 Flag This flag indicates that a high impedance request has been input to the POE0 pin Clear condition: * * By writing 0 to POE0F after reading a POE0F = 1 When the input set by ICSR1 bits 1 and 0 occurs at the POE0 pin Set condition: Rev. 4.00 Dec 05, 2005 page 296 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Initial value All 0 Bit 11 to 9 8 Bit Name R/W R Description Reserved These bits are always read as 0. These bits should always be written with 0 PIE 0 R/W Port Interrupt Enable This bit enables/disables interrupt requests when any of the POE0F to POE3F bits of the ICSR1 are set to 1 0: Interrupt requests disabled 1: Interrupt requests enabled 7 6 POE3M1 POE3M0 0 0 R/W R/W POE3 mode 1, 0 These bits select the input mode of the POE3 pin 00: Accept request on falling edge of POE3 input 01: Accept request when POE3 input has been sampled for 16 P/8 clock pulses, and all are low level. 10: Accept request when POE3 input has been sampled for 16 P/16 clock pulses, and all are low level. 11: Accept request when POE3 input has been sampled for 16 P/128 clock pulses, and all are low level. 5 4 POE2M1 POE2M0 0 0 R/W R/W POE2 mode 1, 0 These bits select the input mode of the POE2 pin 00: Accept request on falling edge of POE2 input 01: Accept request when POE2 input has been sampled for 16 P/8 clock pulses, and all are low level. 10: Accept request when POE2 input has been sampled for 16 P/16 clock pulses, and all are low level. 11: Accept request when POE2 input has been sampled for 16 P/128 clock pulses, and all are low level. 3 2 POE1M1 POE1M0 0 0 R/W R/W POE1 mode 1, 0 These bits select the input mode of the POE1 pin 00: Accept request on falling edge of POE1 input 01: Accept request when POE1 input has been sampled for 16 P/8 clock pulses, and all are low level. 10: Accept request when POE1 input has been sampled for 16 P/16 clock pulses, and all are low level. 11: Accept request when POE1 input has been sampled for 16 P/128 clock pulses, and all are low level. Rev. 4.00 Dec 05, 2005 page 297 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Initial value 0 0 Bit 1 0 Bit Name POE0M1 POE0M0 R/W R/W R/W Description Note: * POE0 mode 1, 0 These bits select the input mode of the POE0 pin 00: Accept request on falling edge of POE0 input 01: Accept request when POE0 input has been sampled for 16 P/8 clock pulses, and all are low level. 10: Accept request when POE0 input has been sampled for 16 P/16 clock pulses, and all are low level. 11: Accept request when POE0 input has been sampled for 16 P/128 clock pulses, and all are low level. The write value should always be 0. Output Level Control/Status Register (OCSR): The output level control/status register (OCSR) is a 16-bit readable/writable register that controls the enable/disable of both output level comparison and interrupts, and indicates status. If the OSF bit is set to 1, the high current pins become high impedance. Bit 15 Bit Name OSF Initial value 0 R/W R/(W)* Description Output Short Flag This flag indicates that any one pair of the three pairs of 2 phase outputs compared have simultaneously become low level outputs. Clear condition: * By writing 0 to OSF after reading an OSF = 1 Set condition: * 14 to 10 All 0 R When any one pair of the three 2-phase outputs simultaneously become low level Reserved These bits are always read as 0. These bits should always be written with 0 Rev. 4.00 Dec 05, 2005 page 298 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Initial value 0 Bit 9 Bit Name OCE R/W R/W Description Output Level Compare Enable This bit enables the start of output level comparisons. When setting this bit to 1, pay attention to the output pin combinations shown in table 10.43, Mode Transition Combinations. When 0 is output, the OSF bit is set to 1 at the same time when this bit is set, and output goes to high impedance. Accordingly, bits 15 to 11 and bit 9 of the port E data register (PEDR) are set to 1. For the MTU output comparison, set the bit to 1 after setting the MTU's output pins with the PFC. Set this bit only when using pins as outputs. When the OCE bit is set to 1, if OIE = 0 a highimpedance request will not be issued even if OSF is set to 1. Therefore, in order to have a high-impedance request issued according to the result of the output level comparison, the OIE bit must be set to 1. When OCE = 1 and OIE = 1, an interrupt request will be generated at the same time as the high-impedance request: however, this interrupt can be masked by means of an interrupt controller (INTC) setting. 0: Output level compare disabled 1: Output level compare enabled; makes an output high impedance request when OSF = 1. 8 OIE 0 R/W Output Short Interrupt Enable This bit makes interrupt requests when the OSF bit of the OCSR is set. 0: Interrupt requests disabled 1: Interrupt request enabled 7 to 0 All 0 R Reserved These bits are always read as 0. These bits should always be written with 0. Note: * The write value should always be 0. Rev. 4.00 Dec 05, 2005 page 299 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) 10.9.4 Operation Input Level Detection Operation If the input conditions set by the ICSR1 occur on any of the POE pins, all high-current pins become high-impedance state. However, only when the general input/output function or MTU function is selected, the large-current pin is in the high-impedance state. Falling Edge Detection: When a change from high to low level is input to the POE pins. Low-Level Detection: Figure 10.115 shows the low-level detection operation. Sixteen continuous low levels are sampled with the sampling clock established by the ICSR1. If even one high level is detected during this interval, the low level is not accepted. Furthermore, the timing when the large-current pins enter the high-impedance state from the sampling clock is the same in both falling-edge detection and in low-level detection. 8/16/128 clock cycles P Sampling clock POE input PE9/ TIOC3B When low level is sampled at all points When high level is sampled at least once High-impedance state* 1 1 2 2 3 16 13 Flag set (POE received) Flag not set Note: * Other large-current pins (PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C, PE15/TIOC4D/IRQOUT) also go to the high-impedance state at the same timing. Figure 10.115 Low-Level Detection Operation Rev. 4.00 Dec 05, 2005 page 300 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) Output-Level Compare Operation Figure 10.116 shows an example of the output-level compare operation for the combination of PE9/TIOC3B and PE11/TIOC3D. The operation is the same for the other pin combinations. P 0 level overlapping detected PE9/ TIOC3B PE11/ TIOC3D High impedance state Figure 10.116 Output-Level Detection Operation Release from High-Impedance State High-current pins that have entered high-impedance state due to input-level detection can be released either by returning them to their initial state with a power-on reset, or by clearing all of the bit 12-15 (POE0F-POE3F) flags of the ICSR1. High-current pins that have become highimpedance due to output-level detection can be released either by returning them to their initial state with a power-on reset, or by first clearing bit 9 (OCE) of the OCSR to disable output-level compares, then clearing the bit 15 (OSF) flag. However, when returning from high-impedance state by clearing the OSF flag, always do so only after outputting a high level from the highcurrent pins (TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D). High-level outputs can be achieved by setting the MTU internal registers. Rev. 4.00 Dec 05, 2005 page 301 of 564 REJ09B0270-0400 Section 10 Multi-Function Timer Pulse Unit (MTU) POE Timing Figure 10.117 shows an example of timing from POE input to high impedance of pin. CK CK falling POE input Falling edge detected PE9/ TIOC3B High impedance state Note: Other large-current pins (PE11/TICO3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C, PE15/TIOC4D/IRQOUT) also goes to the high impedance state at the same timing Figure 10.117 Falling Edge Detection Operation 10.9.5 Usage Note 1. To set the POE pin as a level-detective pin, a high level signal must be firstly input to the POE pin. 2. To clear bits POE0F, POE1F, POE2F, POE3F, and OSF to 0, read registers ICSR1 and OCSR. Clear bits, which are read as 1, to 0, and write 1 to the other bits in the registers. Rev. 4.00 Dec 05, 2005 page 302 of 564 REJ09B0270-0400 Section 11 Watchdog Timer Section 11 Watchdog Timer The watchdog timer (WDT) is an 8-bit timer that can reset this LSI internally if the counter overflows without rewriting the counter value due to a system crash or the like. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. The block diagram of the WDT is shown in figure 11.1. 11.1 Features * Switchable between watchdog timer mode and interval timer mode In watchdog timer mode * Output WDTOVF signal If the counter overflows, it is possible to select whether this LSI is internally reset or not. A power-on reset or manual reset can be selected as an in internal reset. In interval timer mode * If the counter overflows, the WDT generates an interval timer interrupt (ITI). * Clears software standby mode * Selectable from eight counter input clocks. WDT0400A_020020020700 Rev. 4.00 Dec 05, 2005 page 303 of 564 REJ09B0270-0400 Section 11 Watchdog Timer Overflow ITI (interrupt request signal) Interrupt control Clock Clock select WDTOVF Internal reset signal* Reset control /2 /64 /128 /256 /512 /1024 /4096 /8192 Internal clock sources RSTCSR TCNT TSCR Bus interface Module bus WDT Legend: TCSR: Timer control/status register TCNT: Timer counter RSTCSR: Reset control/status register Note: * The internal reset signal can be generated by making a register setting. Power-on reset or manual reset can be selected. Figure 11.1 Block Diagram of WDT 11.2 Input/Output Pin Table 11.1 shows the pin configuration. Table 11.1 Pin Configuration Pin Watchdog timer overflow Note: * Abbreviation WDTOVF* I/O O Function Outputs the counter overflow signal in watchdog timer mode WDTOVF pin should not be pulled-down. If this pin need to be pulled-down, the pulldown resistance value must be 1 M or higher. Rev. 4.00 Dec 05, 2005 page 304 of 564 REJ09B0270-0400 Internal bus Section 11 Watchdog Timer 11.3 Register Descriptions The WDT has the following three registers. For details, refer to appendix A, Internal I/O Register. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, refer to section 11.6.1, Notes on Register Access. * Timer control/status register (TCSR) * Timer counter (TCNT) * Reset control/status register (RSTCSR) 11.3.1 Timer Counter (TCNT) TCNT is an 8-bit readable/writable upcounter. When the timer enable bit (TME) in the timer control/status register (TCSR) is set to 1, TCNT starts counting pulses of an internal clock selected by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the value of TCNT overflows (changes from H'FF to H'00), a watchdog timer overflow signal (WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode selected in the WT/IT bit of TCSR. The initial value of TCNT is H'00. 11.3.2 Timer Control/Status Register (TCSR) TCSR is an 8-bit readable/writable register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. Bit 7 Bit Name OVF Initial Value 0 R/W 1 R/(W)* Description Overflow Flag Indicates that TCNT has overflowed in interval timer mode. Only a write of 0 is permitted, to clear the flag. This flag is not set in watchdog timer mode. [Setting condition] * * * When TCNT overflows in interval timer mode. Cleared after reading OVF When 0 is written to the TME bit in interval timer mode [Clearing conditions] Rev. 4.00 Dec 05, 2005 page 305 of 564 REJ09B0270-0400 Section 11 Watchdog Timer Initial Value 0 Bit 6 Bit Name WT/IT R/W R/W Description Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. When TCNT overflows, the WDT either generates an interval timer interrupt (ITI) or generates a WDTOVF signal, depending on the mode selected. 0: Interval timer mode Interval timer interrupt (ITI) request to the CPU when TCNT overflows 1: Watchdog timer mode WDTOVF signal output externally when TCNT 2 overflows* . 5 TME 0 R/W Timer Enable Enables or disables the timer. 0: Timer disabled TCNT is initialized to H'00 and count-up stops 1: Timer enabled TCNT starts counting. A WDTOVF signal or interrupt is generated when TCNT overflows. 4, 3 All 1 R Reserved This bit is always read as 1, and should only be written with 1. Rev. 4.00 Dec 05, 2005 page 306 of 564 REJ09B0270-0400 Section 11 Watchdog Timer Initial Value 0 0 0 Bit 2 1 0 Bit Name CKS2 CKS1 CKS0 R/W R/W R/W R/W Description Clock Select 2 to 0 Select one of eight internal clock sources for input to TCNT. The clock signals are obtained by dividing the frequency of the system clock (). The overflow 3 frequency for = 40 MHz is enclosed in parentheses* . 000: Clock /2 (period: 12.8 s) 001: Clock /64 (period: 409.6 s) 010: Clock /128 (period: 0.8 ms) 011: Clock /256 (period: 1.6 ms) 100: Clock /512 (period: 3.3 ms) 101: Clock /1024 (period: 6.6 ms) 110: Clock /4096 (period: 26.2 ms) 111: Clock /8192 (period: 52.4 ms) Notes: 1. Only a 0 can be written after reading 1. 2. Section 11.3.3, Reset Control/Status Register (RSTCSR), describes in detail what happens when TCNT overflows in watchdog timer mode. 3. The overflow interval listed is the time from when the TCNT begins counting at H'00 until an overflow occurs. Rev. 4.00 Dec 05, 2005 page 307 of 564 REJ09B0270-0400 Section 11 Watchdog Timer 11.3.3 Reset Control/Status Register (RSTCSR) RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset signal when TCNT overflows. Bit 7 Bit Name WOVF Initial Value 0 R/W R/(W)* Description Watchdog Overflow Flag This bit is set when TCNT overflows in watchdog timer mode. This bit cannot be set in interval timer mode. [Setting condition] * * 6 RSTE 0 R/W Set when TCNT overflows in watchdog timer mode Cleared by reading WOVF, and then writing 0 to WOVF [Clearing condition] Reset Enable Specifies whether or not a reset signal is generated in the chip if TCNT overflows in watchdog timer mode. 0: Reset signal is not generated even if TCNT overflows (Though other peripheral module registers are not reset, TCNT and TCSR in WDT are reset) 1: Reset signal is generated if TCNT overflows 5 RSTS 0 R/W Reset Select Selects the type of internal reset generated if TCNT overflows in watchdog timer mode. 0: Power-on reset 1: Manual reset 4 to 0 All 1 R Reserved These bits are always read as 1, and should only be written with 1. Note: * Only 0 can be written, for flag clearing. Rev. 4.00 Dec 05, 2005 page 308 of 564 REJ09B0270-0400 Section 11 Watchdog Timer 11.4 11.4.1 Operation Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT and TME bits of TCSR to 1. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. No TCNT overflows will occur while the system is operating normally, but if TCNT fails to be rewritten and overflows occur due to a system crash or the like, a WDTOVF signal is output externally. The WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 128 clock cycles. If the RSTE bit in RSTCSR is set to 1, a signal to reset the chip will be generated internally simultaneous to the WDTOVF signal when TCNT overflows. Either a power-on reset or a manual reset can be selected by the RSTS bit in RSTCSR. The internal reset signal is output for 512 clock cycles. When a WDT overflow reset is generated simultaneously with a reset input at the RES pin, the RES reset takes priority, and the WOVF bit in RSTCSR is cleared to 0. The following are not initialized by a WDT reset signal: * POE (port output enable) of MTU and MMT registers * PFC (pin function controller) registers * I/O port registers These registers are initialized only by an external power-on reset. Rev. 4.00 Dec 05, 2005 page 309 of 564 REJ09B0270-0400 Section 11 Watchdog Timer TCNT value Overflow H'FF H'00 WT/IT = 1 TME = 1 H'00 written in TCNT WT/IT = 1 H'00 written TME = 1 in TCNT WDTOVF and internal reset generated WOVF = 1 Time WDTOVF signal Internal reset signal* 128 clocks 512 clocks WT/IT: Timer mode select bit TME: Timer enable bit Note: * Internal reset signal occurs only when the RSTE bit is set to 1. Figure 11.2 Operation in Watchdog Timer Mode Rev. 4.00 Dec 05, 2005 page 310 of 564 REJ09B0270-0400 Section 11 Watchdog Timer 11.4.2 Interval Timer Mode To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1 in TCSR. An interval timer interrupt (ITI) is generated each time the timer counter (TCNT) overflows. This function can be used to generate interval timer interrupts at regular intervals. TCNT value Overflow H'FF Overflow Overflow Overflow H'00 WT/IT = 0 TME = 1 ITI ITI ITI ITI Time ITI: Interval timer interrupt request generation Figure 11.3 Operation in Interval Timer Mode 11.4.3 Clearing Software Standby Mode The watchdog timer has a special function to clear software standby mode with an NMI interrupt or IRQ0 to IRQ3 interrupts. When using software standby mode, set the WDT as described below. Before Transition to Software Standby Mode: The TME bit in TCSR must be cleared to 0 to stop the watchdog timer counter before entering software standby mode. The chip cannot enter software standby mode while the TME bit is set to 1. Set bits CKS2 to CKS0 in TCSR so that the counter overflow interval is equal to or longer than the oscillation settling time. See section 22.3, AC Characteristics. Recovery from Software Standby Mode: When an NMI signal or IRQ0 to IRQ3 signals are received in software standby mode, the clock oscillator starts running and TCNT starts incrementing at the rate selected by bits CKS2 to CKS0 before software standby mode was entered. When TCNT overflows (changes from H'FF to H'00), the clock is presumed to be stable and usable; clock signals are supplied to the entire chip and software standby mode ends. For details on software standby mode, see section 21, Power-Down Modes. Rev. 4.00 Dec 05, 2005 page 311 of 564 REJ09B0270-0400 Section 11 Watchdog Timer 11.4.4 Timing of Setting the Overflow Flag (OVF) In interval timer mode, when TCNT overflows, the OVF bit of TCSR is set to 1 and an interval timer interrupt (ITI) is simultaneously requested. Figure 11.4 shows this timing. TCNT H'FF H'00 Overflow signal (internal signal) OVF Figure 11.4 Timing of Setting OVF 11.4.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF) When TCNT overflows in watchdog timer mode, the WOVF bit of RSTCSR is set to 1 and a WDTOVF signal is output. When the RSTE bit in RSTCSR is set to 1, TCNT overflow enables an internal reset signal to be generated for the entire chip. Figure 11.5 shows this timing. TCNT H'FF H'00 Overflow signal (internal signal) WOVF Figure 11.5 Timing of Setting WOVF Rev. 4.00 Dec 05, 2005 page 312 of 564 REJ09B0270-0400 Section 11 Watchdog Timer 11.5 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (ITI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. Table 11.2 WDT Interrupt Source (in Interval Timer Mode) Name ITI Interrupt Source TCNT overflow Interrupt Flag OVF DTC Activation Impossible 11.6 11.6.1 Usage Notes Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written by a word transfer instruction. They cannot be written by byte transfer instructions. TCNT and TCSR both have the same write address. The write data must be contained in the lower byte of the written word. The upper byte must be H'5A (for TCNT) or H'A5 (for TCSR) (figure 11.6). This transfers the write data from the lower byte to TCNT or TCSR. * Writing to TCNT 15 Address: H'FFFF8610 H'5A 8 7 Write data 0 * Writing to TCSR 15 Address: H'FFFF8610 H'A5 8 7 Write data 0 Figure 11.6 Writing to TCNT and TCSR Rev. 4.00 Dec 05, 2005 page 313 of 564 REJ09B0270-0400 Section 11 Watchdog Timer Writing to RSTCSR: RSTCSR must be written by a word access to address H'FFFF8612. It cannot be written by byte transfer instructions. Procedures for writing 0 to WOVF (bit 7) and for writing to RSTE (bit 6) and RSTS (bit 5) are different, as shown in figure 11.7. To write 0 to the WOVF bit, the write data must be H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0. The RSTE and RSTS bits are not affected. To write to the RSTE and RSTS bits, the upper byte must be H'5A and the lower byte must be the write data. The values of bits 6 and 5 of the lower byte are transferred to the RSTE and RSTS bits, respectively. The WOVF bit is not affected. * Writing 0 to the WOVF bit 15 Address: H'FFFF8612 H'A5 8 7 H'00 0 * Writing to the RSTE and RSTS bits 15 Address: H'FFFF8612 H'5A 8 7 Write data 0 Figure 11.7 Writing to RSTCSR Reading from TCNT, TCSR, and RSTCSR: TCNT, TCSR, and RSTCSR are read like other registers. Use byte transfer instructions. The read addresses are H'FFFF8610 for TCSR, H'FFFF8611 for TCNT, and H'FFFF8613 for RSTCSR. Rev. 4.00 Dec 05, 2005 page 314 of 564 REJ09B0270-0400 Section 11 Watchdog Timer 11.6.2 TCNT Write and Increment Contention If a timer counter increment clock pulse is generated during the T3 state of a write cycle to TCNT, the write takes priority and the timer counter is not incremented. Figure 11.8 shows this operation. TCNT write cycle T1 T2 T3 Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 11.8 Contention between TCNT Write and Increment 11.6.3 Changing CKS2 to CKS0 Bit Values If the values of bits CKS2 to CKS0 in the timer control/status register (TCSR) are rewritten while the WDT is running, the count may not increment correctly. Always stop the watchdog timer (by clearing the TME bit to 0) before rewriting the values of bits CKS2 to CKS0. 11.6.4 Changing between Watchdog Timer/Interval Timer Modes To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0) before switching between interval timer mode and watchdog timer mode. Rev. 4.00 Dec 05, 2005 page 315 of 564 REJ09B0270-0400 Section 11 Watchdog Timer 11.6.5 System Reset by WDTOVF Signal If a WDTOVF output signal is input to the RES pin, the chip cannot initialize correctly. Avoid logical input of the WDTOVF signal to the RES input pin. To reset the entire system with the WDTOVF signal, use the circuit shown in figure 11.9. This LSI Reset input RES Reset signal to entire system WDTOVF Figure 11.9 Example of System Reset Circuit Using WDTOVF Signal 11.6.6 Internal Reset in Watchdog Timer Mode If the RSTE bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally when a TCNT overflow occurs, but TCNT and TCSR in the WDT will be reset. 11.6.7 Manual Reset in Watchdog Timer Mode When an internal reset is effected by TCNT overflow in watchdog timer mode, the processor waits until the end of the bus cycle at the time of manual reset generation before making the transition to manual reset exception processing. Therefore, the bus cycle is retained in a manual reset, but if a manual reset occurs while the bus is released, manual reset exception processing will be deferred until the CPU acquires the bus. However, if the interval from generation of the manual reset until the end of the bus cycle is equal to or longer than the internal manual reset interval of 512 cycles, the internal manual reset source is ignored instead of being deferred, and manual reset exception processing is not executed. 11.6.8 Handling of WDTOVF Pin Do not pull down the WDTOVF pin. If this pin needs to be pulled down, the pull-down resistance value must be 1 M or higher. Rev. 4.00 Dec 05, 2005 page 316 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Section 12 Serial Communication Interface (SCI) This LSI has two independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. In asynchronous serial communication mode, serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). 12.1 Features * Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected External clock can be selected as a transfer clock source. * Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) * Four interrupt sources Four interrupt sources -- transmit-end, transmit-data-empty, receive-data-full, and receive error -- that can issue requests. The transmit-data-empty interrupt and receive data full interrupts can activate the data transfer controller (DTC). * Module standby mode can be set Asynchronous mode * Data length: 7 or 8 bits * Stop bit length: 1 or 2 bits * Parity: Even, odd, or none * Multiprocessor bit: 1 or 0 * Receive error detection: Parity, overrun, and framing errors * Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error SCIS200C_000020020700 Rev. 4.00 Dec 05, 2005 page 317 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Clocked Synchronous mode * Data length: 8 bits * Receive error detection: Overrun errors detected Note: The description in this section are based on LSB-first transfer. Figure 12.1 shows a block diagram of the SCI. Bus interface Module data bus Internal data bus RDR TDR SSR SCR SMR SDCR Transmission/ reception control BRR P Baud rate generator P/8 P/32 P/128 Clock RxD RSR TSR TxD Parity check SCK Parity generation External clock TEI TXI RXI ERI Legend: RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register BRR: Bit rate register SDCR: Serial direction control register Figure 12.1 Block Diagram of SCI Rev. 4.00 Dec 05, 2005 page 318 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) 12.2 Input/Output Pins Table 12.1 shows the serial pins for each SCI channel. Table 12.1 Pin Configuration Channel 2 Pin Name* SCK2 RxD2 TxD2 3 SCK3 RxD3 TxD3 Notes: * I/O I/O Input Output I/O Input Output Function SCI2 clock input/output SCI2 receive data input SCI2 transmit data output SCI3 clock input/output SCI3 receive data input SCI3 transmit data output Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation. 12.3 Register Descriptions The SCI has the following registers for each channel. For details on register addresses and register states during each processing, refer to appendix A, Internal I/O Register. Channel 2 * Serial Mode Register_2 (SMR_2) * Bit Rate Register_2 (BRR_2) * Serial Control Register_2 (SCR_2) * Transmit Data Register_2 (TDR_2) * Serial Status Register_2 (SSR_2) * Receive Data Register_2 (RDR_2) * Serial Direction Control Register_2 (SDCR_2) Channel 3 * Serial Mode Register_3 (SMR_3) * Bit Rate Register_3 (BRR_3) * Serial Control Register_3 (SCR_3) * Transmit Data Register_3 (TDR_3) * Serial Status Register_3 (SSR_3) Rev. 4.00 Dec 05, 2005 page 319 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) * Receive Data Register_3 (RDR_3) * Serial Direction Control Register_3 (SDCR_3) 12.3.1 Receive Shift Register (RSR) RSR is a shift register used to receive serial data that is input to the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU. 12.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores receive data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR is receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous receive operations to be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR for only once. RDR cannot be written to by the CPU. The initial value of RDR is H'00. 12.3.3 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU. 12.3.4 Transmit Data Register (TDR) TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enables continuous serial transmission. If the next transmit data has already been written to TDR during serial transmission, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1. The initial value of TDR is H'FF. Rev. 4.00 Dec 05, 2005 page 320 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) 12.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB (bit 7) of TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (enabled only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (enabled only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit character. 2 MP 0 R/W Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. Rev. 4.00 Dec 05, 2005 page 321 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Initial Value 0 0 Bit 1 0 Bit Name CKS1 CKS0 R/W R/W R/W Description Clock Select 1 and 0 These bits select the clock source for the baud rate generator. 00: P clock (n = 0) 01: P/8 clock (n = 1) 10: P/32 clock (n = 2) 11: P/128 clock (n = 3) For the relation between the bit rate register setting and the baud rate, see section 12.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 12.3.9, Bit Rate Register (BRR)). 12.3.6 Serial Control Register (SCR) SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt requests, and selection of the transfer clock source. For details on interrupt requests, refer to section 12.7, SCI Interrupts. Bit 7 6 Bit Name TIE RIE Initial Value 0 0 R/W R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, TXI interrupt request is enabled. Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. 5 4 TE RE 0 0 R/W R/W Transmit Enable When this bit is set to 1, transmission is enabled. Receive Enable When this bit is set to 1, reception is enabled. Rev. 4.00 Dec 05, 2005 page 322 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Initial Value 0 Bit 3 Bit Name MPIE R/W R/W Description Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, refer to section 12.5, Multiprocessor Communication Function. 2 1 0 TEIE CKE1 CKE0 0 0 0 R/W R/W R/W Transmit End Interrupt Enable This bit is set to 1, TEI interrupt request is enabled. Clock Enable 1 and 0 Selects the clock source and SCK pin function. Asynchronous mode: 00: Internal clock, SCK pin used for input pin (input signal is ignpred) or output pin (output level is undefined) 01: Internal clock, SCK pin used for clock output (The output clock frequency is the same as the bit rate) 10: External clock, SCK pin used for clock input (The input clock frequency is 16 times the bit rate) 11: External clock, SCK pin used for clock input (The input clock frequency is 16 times the bit rate) Clocked synchronous mode: 00: Internal clock, SCK pin used for synchronous clock output 01: Internal clock, SCK pin used for synchronous clock output 10: External clock, SCK pin used for synchronous clock input 11: External clock, SCK pin used for synchronous clock input Rev. 4.00 Dec 05, 2005 page 323 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) 12.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Bit 7 Bit Name TDRE Initial Value 1 R/W R/(W)* Description Transmit Data Register Empty Displays whether TDR contains transmit data. [Setting conditions] * * * Power-on reset or software standby mode When the TE bit in SCR is 0 When data is transferred from TDR to TSR and data can be written to TDR When 0 is written to TDRE after reading TDRE = 1 When the DTC is activated by a TXI interrupt request and transferred data to TDR [Clearing conditions] * * 6 RDRF 0 R/(W)* Receive Data Register Full Indicates that the received data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR Power-on reset or software standby mode When 0 is written to RDRF after reading RDRF = 1 When the DTC is activated by an RXI interrupt and transferred data from RDR [Clearing conditions] * * * The RDRF flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. Rev. 4.00 Dec 05, 2005 page 324 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Initial Value 0 Bit 5 Bit Name ORER R/W R/(W)* Description Overrun Error [Setting condition] * When the next serial reception is completed while RDRF = 1 Power-on reset or software standby mode When 0 is written to ORER after reading ORER = 1 [Clearing conditions] * * The ORER flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. 4 FER 0 R/(W)* Framing Error [Setting condition] * * * When the stop bit is 0 Power-on reset or software standby mode When 0 is written to FER after reading FER = 1 [Clearing conditions] In 2-stop-bit mode, only the first stop bit is checked. The FER flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. 3 PER 0 R/(W)* Parity Error [Setting condition] * * * When a parity error is detected during reception Power-on reset or software standby mode When 0 is written to PER after reading PER = 1 [Clearing conditions] The PER flag is not affected and retains their previous values when the RE bit in SCR is cleared to 0. Rev. 4.00 Dec 05, 2005 page 325 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Initial Value 1 Bit 2 Bit Name TEND R/W R Description Transmit End [Setting conditions] * * * Power-on reset or software standby mode When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1byte serial transmit character When 0 is written to TDRE after reading TDRE = 1 When the DTC is activated by a TXI interrupt and writes data to TDR [Clearing conditions] * * 1 MPB 0 R Multiprocessor Bit MPB stores the multiprocessor bit in the receive data. When the RE bit in SCR is cleared to 0 its previous state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer MPBT sets the multiprocessor bit value to be added to the transmit data. Note: * Only 0 can be written, for flag clearing. Rev. 4.00 Dec 05, 2005 page 326 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) 12.3.8 Serial Direction Control Register (SDCR) The DIR bit in the serial direction control register (SDCR) selects LSB-first or MSB-first transfer. With an 8-bit data length, LSB-first/MSB-first selection is available regardless of the communication mode. With a 7-bit data length, LSB-first transfer must be selected. The description in this section assumes LSB-first transfer. Bit Bit Name Initial Value All 1 R/W R Description Reserved The write value must always be 1. Operation cannot be guaranteed if 0 is written. 3 DIR 0 R/W Data Transfer Direction Selects the serial/parallel conversion format. Valid for an 8-bit transmit/receive format. 0: TDR contents are transmitted in LSB-first order Receive data is stored in RDR in LSB-first 1: TDR contents are transmitted in MSB-first order Receive data is stored in RDR in MSB-first 2 0 R Reserved The write value must always be 0. Operation cannot be guaranteed if 1 is written. 1 0 1 0 R R Reserved This bit is always read as 1, and cannot be modified. Reserved The write value must always be 0. Operation cannot be guaranteed if 1 is written. 7 to 4 12.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 12.2 shows the relationships between the N setting in BRR and the effective bit rate B0 for asynchronous and clocked synchronous modes. The initial value of BRR is H'FF, and it can be read or written to by the CPU at all times. Rev. 4.00 Dec 05, 2005 page 327 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Table 12.2 Relationships between N Setting in BRR and Effective Bit Rate B0 Mode Asynchronous mode (n = 0) Asynchronous mode (n = 1 to 3) Clocked synchronous mode (n = 0) Clocked synchronous mode (n = 1 to 3) Bit Rate B0 = P x 10 6 Error Error (%) = B0 - 1 x 100 B 1 B0 - 1 x 100 B 1 32 x 22n x (N + 1) P x 106 32 x 22n+1 x (N + 1) P x 106 4 x 22n x (N + 1) P x 106 4 x 22n+1 x (N + 1) B0 = Error (%) = B0 = -- B0 = -- Notes: B0: B1: N: P: n: Effective bit rate (bit/s) Actual transfer speed according to the register settings Logical bit rate (bit/s) Specified transfer speed of the target system BRR setting for baud rate generator (0 N 255) Peripheral clock operating frequency (MHz) Determined by the SMR settings shown in the following tables. SMR Setting CKS1 0 0 1 1 CKS0 0 1 0 1 n 0 1 2 3 Table 12.3 shows sample N settings in BRR in normal asynchronous mode. Table 12.4 shows the maximum bit rate for each frequency in normal asynchronous mode. Table 12.6 shows sample N settings in BRR in clocked synchronous mode. For details, refer to section 12.4.2, Receive Data Sampling Timing and Reception Margin in Asynchronous Mode. Tables 12.5 and 12.7 show the maximum bit rates with external clock input. Rev. 4.00 Dec 05, 2005 page 328 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency P (MHz) Logical Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 4 n 1 1 1 1 1 0 0 0 0 0 0 0 0 N 140 103 51 25 12 51 25 12 8 6 3 3 2 Error (%) % 0.74 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -3.55 -6.99 8.51 0.00 8.51 n 1 1 1 1 0 0 0 0 0 0 0 0 0 N 212 155 77 38 155 77 38 19 12 9 6 5 4 6 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.16 -2.34 -6.99 0.00 -2.34 n 2 2 2 2 1 1 0 0 0 0 0 0 0 N 70 51 25 12 25 12 51 25 16 12 8 7 6 8 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 2.12 0.16 -3.55 0.00 -6.99 n 2 2 1 1 1 0 0 0 0 0 0 0 0 N 88 64 129 64 32 129 64 32 21 15 10 9 7 10 Error (%) % -0.25 0.16 0.16 0.16 -1.36 0.16 0.16 -1.36 -1.36 1.73 -1.36 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 106 77 38 77 38 155 77 38 25 19 12 11 9 12 Error (%) % -0.44 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.16 0.00 -2.34 Rev. 4.00 Dec 05, 2005 page 329 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency P (MHz) Logical Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 14 n 2 2 2 2 1 1 0 0 0 0 0 0 0 N 123 90 45 22 45 22 90 45 29 22 14 13 10 Error (%) % 0.23 0.16 -0.93 -0.93 -0.93 -0.93 0.16 -0.93 1.27 -0.93 1.27 0.00 3.57 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 141 103 51 103 51 207 103 51 34 25 16 15 12 16 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -0.79 0.16 2.12 0.00 0.16 n 2 2 2 1 1 0 0 0 0 0 0 0 0 N 159 116 58 116 58 233 116 58 38 28 19 17 14 18 Error (%) % -0.12 0.16 -0.69 0.16 -0.69 0.16 0.16 -0.69 0.16 1.02 -2.34 0.00 -2.34 n 2 2 2 1 1 1 0 0 0 0 0 0 0 N 177 129 64 129 64 32 129 64 42 32 21 19 15 20 Error (%) % -0.25 0.16 0.16 0.16 0.16 -1.36 0.16 0.16 0.94 -1.36 -1.36 0.00 1.73 n 2 2 2 1 1 1 0 0 0 0 0 0 0 N 194 142 71 142 71 35 142 71 47 35 23 21 17 22 Error (%) % 0.16 0.16 -0.54 0.16 -0.54 -0.54 0.16 -0.54 -0.54 -0.54 -0.54 0.00 -0.54 Rev. 4.00 Dec 05, 2005 page 330 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency P (MHz) Logical Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 24 n 2 2 2 1 1 1 0 0 0 0 0 0 0 N 212 155 77 155 77 38 155 77 51 38 25 23 19 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -2.34 n 2 2 2 1 1 1 0 0 0 0 0 0 0 N 221 162 80 162 80 40 162 80 53 40 26 24 19 25 Error (%) % -0.02 -0.15 0.47 -0.15 0.47 -0.76 -0.15 0.47 0.47 -0.76 0.47 0.00 1.73 n 2 2 2 1 1 1 0 0 0 0 0 0 0 N 230 168 84 168 84 41 168 84 55 41 27 25 20 26 Error (%) % -0.08 0.16 -0.43 0.16 -0.43 0.76 0.16 -0.43 0.76 0.76 0.76 0.00 0.76 n 2 2 2 1 1 1 0 0 0 0 0 0 0 N 248 181 90 181 90 45 181 90 60 45 29 27 22 28 Error (%) % -0.17 0.16 0.16 0.16 0.16 -0.93 0.16 0.16 -0.39 -0.93 1.27 0.00 -0.93 n 3 2 2 2 1 1 0 0 0 0 0 0 0 N 66 194 97 48 97 48 194 97 64 48 32 29 23 30 Error (%) % -0.62 0.16 -0.35 -0.35 -0.35 -0.35 0.16 -0.35 0.16 -0.35 -1.36 0.00 1.73 Rev. 4.00 Dec 05, 2005 page 331 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (4) Operating Frequency P (MHz) Logical Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 14400 19200 28800 31250 38400 32 n 3 2 2 2 1 1 0 0 0 0 0 0 0 N 70 207 103 51 103 51 207 103 68 51 34 31 25 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.64 0.16 -0.79 0.00 0.16 n 3 2 2 2 1 1 0 0 0 0 0 0 0 N 74 220 110 54 110 51 220 110 73 54 36 33 27 34 Error (%) % 0.62 0.16 -0.29 0.62 -0.29 6.42 0.16 -0.29 -0.29 0.62 -0.29 0.00 -1.18 n 3 2 2 2 1 1 0 0 0 0 0 0 0 N 79 233 116 58 116 58 234 116 77 58 38 35 28 36 Error (%) % -0.12 0.16 0.16 -0.69 0.16 -0.69 -0.27 0.16 0.16 -0.69 0.16 0.00 1.02 n 3 2 2 2 1 1 0 0 0 0 0 0 0 N 83 246 123 61 123 61 246 123 81 61 40 37 30 38 Error (%) % 0.40 0.16 -0.24 -0.24 -0.24 -0.24 0.16 -0.24 0.57 -0.24 0.57 0.00 -0.24 n 3 3 2 2 1 1 1 0 0 0 0 0 0 N 88 64 129 64 129 64 32 129 86 64 42 39 32 40 Error (%) % -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 0.16 -0.22 0.16 0.94 0.00 -1.36 Rev. 4.00 Dec 05, 2005 page 332 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Table 12.4 Maximum Bit Rate for Each Frequency when Using Baud Rate Generator (Asynchronous Mode) P (MHz) 4 8 10 12 14 16 18 20 22 24 25 26 28 30 32 34 36 38 40 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Maximum Bit Rate (bit/s) 125000 250000 312500 375000 437500 500000 562500 625000 687500 750000 781250 812500 875000 937500 1000000 1062500 1125000 1187500 1250000 Rev. 4.00 Dec 05, 2005 page 333 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Table 12.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) P (MHz) 4 6 8 10 12 14 16 18 20 22 24 25 26 28 30 32 34 36 38 40 External Clock (MHz) 1.0000 1.5000 2.0000 2.5000 3.0000 3.5000 4.0000 4.5000 5.0000 5.5000 6.0000 6.2500 6.5000 7.0000 7.5000 8.0000 8.5000 9.0000 9.5000 10.0000 Maximum Bit Rate (bit/s) 62500 93750 125000 156250 187500 218750 250000 281250 312500 343750 375000 390625 406250 437500 468750 500000 531250 562500 593750 625000 Rev. 4.00 Dec 05, 2005 page 334 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1) Operating Frequency P (MHz) Logical Bit Rate (bit/s) 250 500 1000 2500 5000 10000 25000 50000 100000 250000 500000 1000000 2500000 5000000 4 n 2 1 1 1 1 0 0 0 0 0 0 0 -- -- N 124 249 124 49 24 99 39 19 9 3 1 0* -- -- n 2 2 1 1 -- 0 0 0 0 0 0 -- -- -- 6 N 187 93 187 74 -- 149 59 29 14 5 2 -- -- -- n 2 2 1 1 1 1 1 1 0 0 0 0 -- -- 8 N 249 124 249 99 49 24 9 4 19 7 3 1 -- -- n 3 2 2 1 1 0 0 0 0 0 0 -- 0 -- 10 N 77 155 77 124 61 249 99 49 24 9 4 -- 0* -- n 3 2 2 1 1 -- 1 0 0 0 0 0 -- -- 12 N 93 187 93 149 74 -- 14 59 29 11 5 2 -- -- Rev. 4.00 Dec 05, 2005 page 335 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2) Operating Frequency P (MHz) Logical Bit Rate (bit/s) 14 n N n 16 N n 18 N n 20 N n 22 N 250 500 1000 2500 5000 10000 25000 50000 100000 250000 500000 1000000 2500000 5000000 3 2 2 1 1 1 0 0 0 0 0 -- -- -- 108 218 108 174 86 43 139 69 34 13 6 -- -- -- 3 2 2 2 2 1 1 1 1 1 1 0 -- -- 124 249 124 49 24 49 19 9 4 1 0 3 -- -- 3 3 2 1 1 1 0 0 0 0 0 -- -- -- 140 69 140 224 112 55 179 89 44 17 8 -- -- -- 3 3 2 1 1 1 1 0 0 0 0 0 0 0 155 77 155 249 124 62 24 99 49 19 9 4 1 0* 3 3 3 2 1 1 0 0 0 0 0 -- -- -- 171 85 42 68 137 68 219 109 54 21 10 -- -- -- Rev. 4.00 Dec 05, 2005 page 336 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (3) Operating Frequency P (MHz) Logical Bit Rate (bit/s) 250 500 1000 2500 5000 10000 25000 50000 100000 250000 500000 1000000 2500000 5000000 24 n 3 3 2 2 1 1 1 1 0 0 0 0 -- -- N 187 93 187 74 149 74 29 14 59 23 11 5 -- -- n 3 3 2 2 1 1 0 0 0 0 -- -- -- -- 25 N 194 97 194 77 155 77 249 124 62 24 -- -- -- -- n 3 3 2 2 1 1 -- 0 0 0 0 -- -- -- 26 N 202 101 202 80 162 80 -- 129 64 25 12 -- -- -- n 3 3 2 2 1 1 1 0 0 0 0 0 -- -- 28 N 218 108 218 86 174 86 34 139 69 27 13 6 -- -- n 3 3 2 2 1 1 -- 0 0 0 0 -- 0 -- 30 N 233 116 233 93 187 93 -- 149 74 29 14 -- 2 -- Rev. 4.00 Dec 05, 2005 page 337 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (4) Operating Frequency P (MHz) Logical Bit Rate (bit/s) 250 500 1000 2500 5000 10000 25000 50000 100000 250000 500000 1000000 2500000 5000000 32 n 3 3 2 2 2 2 2 2 1 1 1 1 -- -- N 249 124 249 99 49 24 9 4 9 3 1 0 -- -- n -- 3 3 2 1 1 -- 0 0 0 0 -- -- -- 34 N -- 132 65 105 212 105 -- 169 84 33 16 -- -- -- n -- 3 3 2 1 1 1 0 0 0 0 0 -- -- 36 N -- 140 69 112 224 112 44 179 89 35 17 8 -- -- n -- 3 3 2 1 1 -- 0 0 0 0 -- -- -- 38 N -- 147 73 118 237 118 -- 189 94 37 18 -- -- -- n -- 3 3 2 1 1 1 1 0 0 0 0 0 0 40 N -- 155 77 124 249 124 49 24 99 39 19 9 3 1 Rev. 4.00 Dec 05, 2005 page 338 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Table 12.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) P (MHz) 4 6 8 10 12 14 16 18 20 22 24 25 26 28 30 32 34 36 38 40 External Clock (MHz) 0.6667 1.0000 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 3.6667 4.0000 4.1667 4.3333 4.6667 5.0000 5.3333 5.6667 6.0000 6.3333 6.6667 Maximum Bit Rate (bit/s) 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3 3666666.7 4000000.0 4166666.7 4333333.3 4666666.7 5000000.0 5333333.3 5666666.7 6000000.0 6333333.3 6666666.7 Legend: -- : Can be set, but there will be a degree of error. * : Continuous transfer is not possible. Note: Settings with an error of 1% or less are recommended. Rev. 4.00 Dec 05, 2005 page 339 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) 12.4 Operation in Asynchronous Mode Figure 12.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data, a parity bit, and finally stop bits (high level). In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Idle state (mark state) 1 LSB 0 Start bit 1 bit D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 bit or none 1 1 1 Serial data Transmit/receive data 7 or 8 bits Stop bit 1 or 2 bits One unit of transfer data (character or frame) Figure 12.2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) 12.4.1 Data Transfer Format Table 12.8 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, refer to section 12.5, Multiprocessor Communication Function. Rev. 4.00 Dec 05, 2005 page 340 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Table 12.8 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 PE 0 MP 0 STOP 0 1 S 2 Serial Transfer Format and Frame Length 3 4 5 6 7 8 9 10 11 12 8-bit data STOP 0 0 0 1 S 8-bit data STOP STOP 0 1 0 0 S 8-bit data P STOP 0 1 0 1 S 8-bit data P STOP STOP 1 0 0 0 S 7-bit data STOP 1 0 0 1 S 7-bit data STOP STOP 1 1 0 0 S 7-bit data P STOP 1 1 0 1 S 7-bit data P STOP STOP 0 X 1 0 S 8-bit data MPB STOP 0 X 1 1 S 8-bit data MPB STOP STOP 1 X 1 0 S 7-bit data MPB STOP 1 X 1 1 S 7-bit data MPB STOP STOP Legend: S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit X: Don't care Rev. 4.00 Dec 05, 2005 page 341 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) 12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 12.3. Thus the reception margin in asynchronous mode is given by formula (1) below. M= 0.5 - 1 (D - 0.5) - - (L - 0.5) F 2N N x 100% ........................... Formula (1) Where M: N: D: L: F: Reception margin (%) Ratio of bit rate to clock (N = 16) Clock duty (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute value of clock rate deviation Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin is given by formula below. M = {0.5 - 1/(2 x 16)} x 100 [%] = 46.875% However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. 16 clocks 8 clocks 0 7 15 0 7 15 0 Internal basic clock Receive data (RxD) Synchronization sampling timing Data sampling timing Start bit D0 D1 Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode Rev. 4.00 Dec 05, 2005 page 342 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) 12.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 12.4. The clock must not be stopped during operation. SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 12.4 Relation between Output Clock and Transmit Data Phase (Asynchronous Mode) Rev. 4.00 Dec 05, 2005 page 343 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) 12.4.4 SCI initialization (Asynchronous mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization. Start transmission Clear RIE, TIE, TEIE, MPIE,* TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) Set data transfer format in SMR Set value in BRR Wait [1] [2] [3] No 1-bit interval elapsed? Yes Set PFC of the external pin used SCK, TxD, RxD Set RIE, TIE, TEIE, and MPIE bits Set TE and RE bits in SCR to 1 < Initialization completion> [4] [1] Set the clock selection in SCR. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Set PFC of the external pin used. Set RxD input during receiving and TxD output during transmitting. Set SCK input/output according to contents set by CKE1 and CKE0. When CKE1 and CKE0 are 0 in asynchronous mode, setting the SCK pin is unnecessary. Outputting clocks from the SCK pin starts at synchronous clock output setting. [5] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1.* At this time, the TxD, RxD, and SCK pins can be used. The TxD pin is in a mark state during transmitting, and RxD pin is in an idle state for waiting the start bit during receiving. [5] Note: * In simultaneous transmit/receive operation, the TE and RE bits must be cleared to 0 or set to 1 simultaneously. Figure 12.5 Sample SCI Initialization Flowchart Rev. 4.00 Dec 05, 2005 page 344 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) 12.4.5 Data transmission (Asynchronous mode) Figure 12.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request (TXI) is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 12.7 shows a sample flowchart for transmission in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 TxD 1 Idle state (mark state) TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt processing routine frame TXI interrupt request generated TEI interrupt request generated Figure 12.6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 4.00 Dec 05, 2005 page 345 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Initialization Start transmission [1] Read TDRE flag in SSR No [2] [1] SCI initialization: Set the TxD pin using the PFC. After the TE bit is set to 1, 1 is output for one frame, and transmission is enabled. However, data is not transmitted. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, first clear the port data register (DR) to 0, then clear the TE bit to 0 in SCR and use the PFC to select the TxD pin as an output port. TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 All data transmitted? Yes No [3] Read TEND flag in SSR No TEND = 1 Yes Break output? Yes Clear DR to 0 No [4] Clear TE bit in SCR to 0; select the TxD pin as an output port with the PFC Figure 12.7 Sample Serial Transmission Flowchart Rev. 4.00 Dec 05, 2005 page 346 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) 12.4.6 Serial data reception (Asynchronous mode) Figure 12.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt processing routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 RxD 1 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine ERI interrupt request generated by framing error 1 frame Figure 12.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) Rev. 4.00 Dec 05, 2005 page 347 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Table 12.9 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 12.9 shows a sample flow chart for serial data reception. Table 12.9 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * OER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error The RDRF flag retains its state before data reception. Rev. 4.00 Dec 05, 2005 page 348 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Initialization Start reception [1] [1] SCI initialization: Set the RxD pin using the PFC. [2] [3] Receive error processing and break detection: If a receive error occurs, read the ORER, PER, and FER flags in SSR to Read ORER, PER, and [2] identify the error. After performing the FER flags in SSR appropriate error processing, ensure that the ORER, PER, and FER flags are Yes all cleared to 0. Reception cannot be PERFERORER = 1 resumed if any of these flags are set to [3] 1. In the case of a framing error, a No Error processing break can be detected by reading the value of the input port corresponding to (Continued on next page) the RxD pin. Read RDRF flag in SSR No [4] [4] SCI status check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when DTC is activated by an RXI interrupt and the RDR value is read. RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 [5] Figure 12.9 Sample Serial Reception Data Flowchart (1) Rev. 4.00 Dec 05, 2005 page 349 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) [3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? No Framing error processing Clear RE bit in SCR to 0 Yes No PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 12.9 Sample Serial Reception Data Flowchart (2) Rev. 4.00 Dec 05, 2005 page 350 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) 12.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 12.10 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends the ID code of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and OER to 1 are inhibited until data with a 1 multiprocessor bit is received. On reception of receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode. Rev. 4.00 Dec 05, 2005 page 351 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Transmitting station Serial transmission line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) H'01 (MPB = 1) ID transmission cycle = receiving station specification H'AA (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 12.10 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) 12.5.1 Multiprocessor Serial Data Transmission Figure 12.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode. Rev. 4.00 Dec 05, 2005 page 352 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Initialization Start transmission Read TDRE flag in SSR No [1] [2] [1] SCI initialization: Set the TxD pin using the PFC. After the TE bit is set to 1, 1 is output for one frame, and transmission is enabled. However, data is not transmitted. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, first clear the port data register (DR) to 0, then clear the TE bit to 0 in SCR and use the PFC to select the TxD pin as an output port. TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 All data transmitted? Yes Read TEND flag in SSR No [3] TEND = 1 Yes Break output? Yes Clear DR to 0 No No [4] Clear TE bit in SCR to 0; select the TxD pin as an output port with the PFC Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart Rev. 4.00 Dec 05, 2005 page 353 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) 12.5.2 Multiprocessor Serial Data Reception Figure 12.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 12.12 shows an example of SCI operation for multiprocessor format reception. Start bit 0 D0 Data (ID1) MPB D1 D7 1 Stop bit 1 Start bit 0 D0 Data (Data1) D1 D7 Stop MPB bit 0 1 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated ID1 RDR data read If not this station's ID, and RDRF flag MPIE bit is set to 1 cleared to 0 in again RXI interrupt processing routine RXI interrupt request is not generated, and RDR retains its state (a) Data does not match station's ID 1 Start bit 0 D0 Data (ID2) D1 D7 Stop MPB bit 1 1 Start bit 0 D0 Data (Data2) D1 D7 Stop MPB bit 0 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine ID2 Data2 Matches this station's ID, MPIE bit is set to 1 so reception continues, again and data is received in RXI interrupt processing routine (b) Data matches station's ID Figure 12.12 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) Rev. 4.00 Dec 05, 2005 page 354 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Initialization Start reception Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR FERORER = 1 No Read RDRF flag in SSR No [1] [1] SCI initialization: Set the RxD pin using the PFC. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [2] Yes [3] [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are all cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. [4] RDRF = 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR FERORER = 1 No Read RDRF flag in SSR No Yes RDRF = 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error processing (Continued on next page) Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1) Rev. 4.00 Dec 05, 2005 page 355 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) [5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? No Framing error processing Clear RE bit in SCR to 0 Yes Clear ORER and FER flags in SSR to 0 Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 4.00 Dec 05, 2005 page 356 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) 12.6 Operation in Clocked Synchronous Mode Figure 12.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. Data is transferred in 8-bit units. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * Figure 12.14 Data Format in Clocked Synchronous Communication (For LSB-First) 12.6.1 Clock Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed, the clock is fixed high. Only in reception, the serial clock is continued generating until an overrun error is occurred or the RE bit is cleared to 0. To execute reception in one-character units, select an external clock as a clock source. 12.6.2 SCI initialization (Clocked Synchronous mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 12.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1. Rev. 4.00 Dec 05, 2005 page 357 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Note that clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags, or the contents of RDR. [1] Set the clock selection in SCR. [2] Set the data transfer format in SMR. Clear RIE, TIE, TEIE, MPIE, TE and RE bits in SCR to 0* Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0) Set data transfer format in SMR Set value in BRR Wait No Start initialization [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [1] [4] Set PFC of the external pin used. Set RxD input during receiving and TxD output during transmitting. Set SCK input/output according to contents set by CKE1 and CKE0. [5] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1.* At this time, the TxD, RxD, and SCK pins can be used. The TxD pin is in a mark state during transmitting. When synchronous clock output (clock master) is set during receiving in synchronous mode, outputting clocks from the SCK pin starts. [2] [3] 1-bit interval elapsed? Yes Set PFC of the external pin used SCK, TxD, RxD Set RIE, TIE, and TEIE bits Set TE and RE bits in SCR to 1 [4] [5] Note: * In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 12.15 Sample SCI Initialization Flowchart 12.6.3 Serial data transmission (Clocked Synchronous mode) Figure 12.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a transmit data empty (TXI) Rev. 4.00 Dec 05, 2005 page 358 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) interrupt request is generated. Because the TXI interrupt routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). 5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 12.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags. Transfer direction Synchronization clock Serial data Bit 0 Bit 1 Bit 0 Bit 4 Bit 5 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt processing routine 1 frame TXI interrupt request generated TEI interrupt request generated Figure 12.16 Sample SCI Transmission Operation in Clocked Synchronous Mode Rev. 4.00 Dec 05, 2005 page 359 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Initialization Start transmission [1] [1] SCI initialization: Set the TxD pin using the PFC. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Read TDRE flag in SSR No [2] TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 All data transmitted? Yes Read TEND flag in SSR No [3] TEND = 1 Yes Clear TE bit in SCR to 0 No Figure 12.17 Sample Serial Transmission Flowchart Rev. 4.00 Dec 05, 2005 page 360 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) 12.6.4 Serial data reception (Clocked Synchronous mode) Figure 12.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the received data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt processing routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled. Synchronization clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 12.18 Example of SCI Operation in Reception Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 12.19 shows a sample flowchart for serial data reception. Rev. 4.00 Dec 05, 2005 page 361 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Initialization Start reception [1] [1] SCI initialization: Set the RxD pin using the PFC. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. Read ORER flag in SSR Yes [2] ORER = 1 No [3] No [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive (Continued below) data in RDR and clear the RDRF flag Read RDRF flag in SSR [4] to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. RDRF = 1 Error processing Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished. The RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. No All data received? Yes Clear RE bit in SCR to 0 [5] [3] Error processing Overrun error processing Clear ORER flag in SSR to 0 Figure 12.19 Sample Serial Reception Flowchart Rev. 4.00 Dec 05, 2005 page 362 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) 12.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous mode) Figure 12.20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations after the SCI initialization. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear RE to 0. Then after checking that the RDRF and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction. Rev. 4.00 Dec 05, 2005 page 363 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Initialization Start transmission/reception [1] [1] SCI initialization: Set the TxD and RxD pins using the PFC. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. Read TDRE flag in SSR No [2] TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 Read ORER flag in SSR Yes [3] Error processing [4] ORER = 1 No Read RDRF flag in SSR No RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear TE and RE bits in SCR to 0 [5] Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. Figure 12.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations Rev. 4.00 Dec 05, 2005 page 364 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) 12.7 12.7.1 SCI Interrupts Interrupts in Normal Serial Communication Interface Mode Table 12.10 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt request can activate the DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is performed by the DTC. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt request can activate the DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC. A TEI interrupt is generated when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are generated simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later. Table 12.10 SCI Interrupt Sources Channel 2 Name ERI_2 RXI_2 TXI_2 TEI_2 3 ERI_3 RXI_3 TXI_3 TEI_3 Interrupt Source Receive Error Receive Data Full Transmit Data Empty Transmission End Receive Error Receive Data Full Transmit Data Empty Transmission End Interrupt Flag ORER, FER, PER RDRF TDRE TEND ORER, FER, PER RDRF TDRE TEND DTC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Rev. 4.00 Dec 05, 2005 page 365 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) 12.8 12.8.1 Usage Notes TDR Write and TDRE Flag The TDRE bit in the serial status register (SSR) is a status flag indicating transferring of transmit data from TDR into TSR. The SCI sets the TDRE bit to 1 when it transfers data from TDR to TSR. Data can be written to TDR regardless of the TDRE bit status. If new data is written in TDR when TDRE is 0, however, the old data stored in TDR will be lost because the data has not yet been transferred to TSR. Before writing transmit data to TDR, be sure to check that the TDRE bit is set to 1. 12.8.2 Module Standby Mode Setting SCI operation can be disabled or enabled using the module standby control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 21, Power-Down Modes. 12.8.3 Break Detection and Processing (Asynchronous Mode Only) When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 12.8.4 Sending a Break Signal (Asynchronous Mode Only) The TxD pin becomes of the I/O port general I/O pin with the I/O direction and level determined by the port data register (DR) and the port I/O register (IOR) of the pin function controller (PFC). These conditions allow break signals to be sent. The DR value is substituted for the marking status until the PFC is set. Consequently, the output port is set to initially output a 1. To send a break in serial transmission, first clear the DR to 0, then establish the TxD pin as an output port using the PFC. When the TE bit is cleared to 0, the transmission section is initialized regardless of the present transmission status. Rev. 4.00 Dec 05, 2005 page 366 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) 12.8.5 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. 12.8.6 Constraints on DTC Use 1. When using an external clock source for the serial clock, update TDR with the DTC, and then after the elapse of five peripheral clocks (P) or more, input a transmit clock. If a transmit clock is input in the first four P clocks after TDR is written, an error may occur (figure 12.21). 2. Before reading the receive data register (RDR) with the DTC, select the receive-data-full (RXI) interrupt of the SCI as a start-up source. SCK t TDRE D0 D1 D2 D3 D4 D5 D6 D7 Note: During external clock operation, an error may occur if t is 4 P clocks or less. Figure 12.21 Example of Clocked Synchronous Transmission with DTC 12.8.7 Cautions on Clocked Synchronous External Clock Mode 1. Set TE = RE = 1 only when external clock SCK is 1. 2. Do not set TE = RE = 1 until at least four P clocks after external clock SCK has changed from 0 to 1. 3. When receiving, RDRF is 1 when RE is cleared to 0 after 2.5-3.5 P clocks from the rising edge of the RxD D7 bit SCK input, but copying to RDR is not possible. 12.8.8 Caution on Clocked Synchronous Internal Clock Mode When receiving, RDRF is 1 when RE is cleared to 0 after 1.5 P clocks from the rising edge of the RxD D7 bit SCK output, but copying to RDR is not possible. Rev. 4.00 Dec 05, 2005 page 367 of 564 REJ09B0270-0400 Section 12 Serial Communication Interface (SCI) Rev. 4.00 Dec 05, 2005 page 368 of 564 REJ09B0270-0400 Section 13 A/D Converter Section 13 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter. The block diagram of the A/D converter is shown in figure 13.1. 13.1 Features * 10-bit resolution * Input channels 12 channels (three independent A/D conversion modules) * Conversion time: 6.7 s per channel (at P = 20 MHz operation), 5.4 s (during P = 25 MHz operation) * Three operating modes Single mode: Single-channel A/D conversion Continuous scan mode: Repetitive A/D conversion on 1 to 4 channels Single-cycle scan mode: Continuous A/D conversion on 1 to 4 channels * Data registers Conversion results are held in a 16-bit data register for each channel * Sample and hold function * Three methods for conversion start Software Conversion start trigger from multifunction timer pulse unit (MTU) or motor management timer (MMT) External trigger signal * Interrupt request An A/D conversion end interrupt request (ADI) can be generated * Module stop mode can be set ADCMS20C_000020020700 Rev. 4.00 Dec 05, 2005 page 369 of 564 REJ09B0270-0400 Section 13 A/D Converter Module data bus Bus interface ADDRm ADCSR ADDRn ADTSR ADCR * * * Internal data bus AVCC 10-bit D/A AVSS Successive approximations register + ANm * P/4 P/8 Comparator Multiplexer Control circuit * * * * * P/16 P/32 Sample-andhold circuit ANn ADI interrupt signal Conversion start trigger from MTU/MMT ADTRG Legend: ADCR: A/D control register ADCSR: A/D control/status register ADTSR: A/D trigger select register ADDRm-ADDRn: A/D data register m to n Note: The register number corresponds to the channel number of the module. (m = 8, n = 19) Figure 13.1 Block Diagram of A/D Converter (For One Module) Rev. 4.00 Dec 05, 2005 page 370 of 564 REJ09B0270-0400 Section 13 A/D Converter 13.2 Input/Output Pins Table 13.1 summarizes the input pins used by the A/D converter. This LSI has three A/D conversion modules each of which can be operated independently. The input channels are divided into four channel sets. Table 13.1 Pin Configuration Module Type Common Pin Name AVCC AVSS ADTRG A/D module 0 (A/D0) AN8 AN9 AN10 AN11 A/D module 1 (A/D1) AN12 AN13 AN14 AN15 A/D module 2 (A/D2) AN16 AN17 AN18 AN19 I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Function Analog block power supply and reference voltage Analog block ground and reference voltage A/D external trigger input pin Analog input pin 8 Analog input pin 9 Analog input pin 10 Analog input pin 11 Analog input pin 12 Analog input pin 13 Analog input pin 14 Analog input pin 15 Analog input pin 16 Analog input pin 17 Analog input pin 18 Analog input pin 19 Group 0 Group 1 Group 1 Note: The connected A/D module differs for each pin. The control registers of each module must be set. Rev. 4.00 Dec 05, 2005 page 371 of 564 REJ09B0270-0400 Section 13 A/D Converter 13.3 Register Description The A/D converter has the following registers. For details on register addresses, refer to appendix A, Internal I/O Register. * A/D data register 8 (H/L) (ADDR8) * A/D data register 9 (H/L) (ADDR9) * A/D data register 10 (H/L) (ADDR10) * A/D data register 11 (H/L) (ADDR11) * A/D data register 12 (H/L) (ADDR12) * A/D data register 13 (H/L) (ADDR13) * A/D data register 14 (H/L) (ADDR14) * A/D data register 15 (H/L) (ADDR15) * A/D data register 16 (H/L) (ADDR16) * A/D data register 17 (H/L) (ADDR17) * A/D data register 18 (H/L) (ADDR18) * A/D data register 19 (H/L) (ADDR19) * A/D control/status register_0 (ADCSR_0) * A/D control/status register_1 (ADCSR_1) * A/D control/status register_2 (ADCSR_2) * A/D control register_0 (ADCR_0) * A/D control register_1 (ADCR_1) * A/D control register_2 (ADCR_2) * A/D trigger select register (ADTSR) 13.3.1 A/D Data Registers 8 to 19 (ADDR8 to ADDR19) ADDRs are 16-bit read-only registers. The conversion result for each analog input channel is stored in ADDR with the corresponding number. (For example, the conversion result of AN8 is stored in ADDR8.) The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0. The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read directly from the CPU, however the lower byte should be read via a temporary register. The temporary register contents are transferred from the ADDR when the upper byte data is read. When reading the ADDR, read the upper byte before the lower byte, or read in word unit. The initial value of ADDR is H'0000. Rev. 4.00 Dec 05, 2005 page 372 of 564 REJ09B0270-0400 Section 13 A/D Converter 13.3.2 A/D Control/Status Registers 0 to 2 (ADCSR_0 to ADCSR_2) ADCSR for each module controls A/D conversion operations. Bit 7 Bit Name ADF Initial Value 0 R/W R/(W)* Description A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * * When A/D conversion ends in single mode When A/D conversion ends on all specified channels in scan mode When 0 is written after reading ADF = 1 When the DTC is activated by an ADI interrupt and ADDR is read with the DISEL bit in DTMR of DTC = 0 [Clearing conditions] * * 6 ADIE 0 R/W A/D Interrupt Enable The A/D conversion end interrupt (ADI) request is enabled when 1 is set When changing the operating mode, first clear the ADST bit in the A/D control registers (ADCRs) to 0. 5 4 ADM1 ADM0 0 0 R/W R/W A/D Mode 1 and 0 Select the A/D conversion mode. 00: Single mode 01: 4-channel scan mode 10: Setting prohibited 11: Setting prohibited When changing the operating mode, first clear the ADST bit in the A/D control registers (ADCRs) to 0. 3 1 R Reserved This bit is always read as 1, and should only be written with 1. 2 1 0 Note: CH2 CH1 CH0 * 0 0 0 R/W R/W R/W Channel Select 2 to 0 Select analog input channels. See table 13.2. When changing the operating mode, first clear the ADST bit in the A/D control registers (ADCRs) to 0. Only 0 can be written to clear the flag. Rev. 4.00 Dec 05, 2005 page 373 of 564 REJ09B0270-0400 Section 13 A/D Converter Table 13.2 Channel Select List Analog Input Channels Bit 2 CH2 0 Bit 1 CH1 0 Bit 0 CH0 0 1 1 0 1 1 0 0 1 1 0 1 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 A/D0 Setting prohibited Single Mode A/D1 Setting prohibited A/D2 AN16 AN17 AN18 AN19 Setting prohibited AN8 AN8, AN9 AN12 AN12, AN13 A/D0 Setting prohibited 4-Channel Scan Mode* A/D1 Setting prohibited A/D2 AN16 AN16, AN17 AN16 to AN18 AN16 to AN19 Setting prohibited AN8 to AN10 AN12 to AN14 AN8 to AN11 AN12 to AN15 Notes: * Continuous scan mode or single-cycle scan mode can be selected with the ADCS bit. 13.3.3 A/D Control Registers_0 to 2 (ADCR_0 to ADCR_2) ADCR for each module controls A/D conversion started by an external trigger signal and selects the operating clock. Bit 7 Bit Name TRGE Initial Value 0 R/W R/W Description Trigger Enable Enables or disables triggering of A/D conversion by ADTRG, an MTU trigger, or an MMT trigger. 0: A/D conversion triggering is disabled 1: A/D conversion triggering is enabled 6 5 CKS1 CKS0 0 0 R/W R/W Clock Select 0 and 1 Select the A/D conversion time. 00: P/32 01: P/16 10: P/8 11: P/4 When changing the A/D conversion time, first clear the ADST bit in the A/D control registers (ADCRs) to 0. CKS[1,0] = b'11 can be set while P 25 MHz. Rev. 4.00 Dec 05, 2005 page 374 of 564 REJ09B0270-0400 Section 13 A/D Converter Initial Value 0 Bit 4 Bit Name ADST R/W R/W Description A/D Start Starts or stops A/D conversion. When this bit is set to 1, A/D conversion is started. When this bit is cleared to 0, A/D conversion is stopped and the A/D converter enters the idle state. In single or single-cycle scan mode, this bit is automatically cleared to 0 when A/D conversion ends on the selected single channel. In continuous scan mode, A/D conversion is continuously performed for the selected channels in sequence until this bit is cleared by a software, reset, or in software standby mode or module standby mode. 3 ADCS 0 R/W A/D Continuous Scan Selects either single-cycle scan or continuous scan in scan mode. This bit is valid only when scan mode is selected. 0: Single-cycle scan 1: Continuous scan When changing the operating mode, first clear the ADST bit in the A/D control registers (ADCRs) to 0. 2 to 0 All 1 R Reserved These bits are always read as 1, and should only be written with 1. Rev. 4.00 Dec 05, 2005 page 375 of 564 REJ09B0270-0400 Section 13 A/D Converter 13.3.4 A/D Trigger Select Register (ADTSR) The ADTSR enables an A/D conversion started by an external trigger signal. Bit 7, 6 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0, and should only be written with 0. 5 4 TRG2S1 TRG2S0 0 0 R/W R/W AD Trigger 2 Select 1 and 0 Enable the start of A/D conversion by A/D2 with a trigger signal. 00: A/D conversion start by external trigger pin (ADTRG) or MTU trigger is enabled 01: A/D conversion start by external trigger pin (ADTRG) is enabled 10: A/D conversion start by MTU trigger is enabled 11: A/D conversion start by MMT trigger is enabled When changing the operating mode, first clear the TRGE and ADST bit in the A/D control registers (ADCRs) to 0. 3 2 TRG1S1 TRG1S0 0 0 R/W R/W AD Trigger 1 Select 1 and 0 Enable the start of A/D conversion by A/D1 with a trigger signal. 00: A/D conversion start by external trigger pin (ADTRG) or MTU trigger is enabled 01: A/D conversion start by external trigger pin (ADTRG) is enabled 10: A/D conversion start by MTU trigger is enabled 11: A/D conversion start by MMT trigger is enabled When changing the operating mode, first clear the TRGE and ADST bit in the A/D control registers (ADCRs) to 0. Rev. 4.00 Dec 05, 2005 page 376 of 564 REJ09B0270-0400 Section 13 A/D Converter Initial Value 0 0 Bit 1 0 Bit Name TRG0S1 TRG0S0 R/W R/W R/W Description AD Trigger 0 Select 1 and 0 Enable the start of A/D conversion by A/D0 with a trigger signal. 00: A/D conversion start by external trigger pin (ADTRG) or MTU trigger is enabled 01: A/D conversion start by external trigger pin (ADTRG) is enabled 10: A/D conversion start by MTU trigger is enabled 11: A/D conversion start by MMT trigger is enabled When changing the operating mode, first clear the TRGE and ADST bit in the A/D control registers (ADCRs) to 0. 13.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. There are two kinds of scan mode: continuous mode and single-cycle mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the ADST bit to 0 in ADCR. The ADST bit can be set at the same time when the operating mode or analog input channel is changed. 13.4.1 Single Mode In single mode, A/D conversion is to be performed only once on the specified single channel. The operations are as follows. 1. A/D conversion is started when the ADST bit in ADCR is set to 1, according to software, MTU, MMT, or external trigger input. 2. When A/D conversion is completed, the result is transferred to the A/D data register corresponding to the channel. 3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains set to 1 during A/D conversion. When A/D converion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the idle state. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters the idle state. Rev. 4.00 Dec 05, 2005 page 377 of 564 REJ09B0270-0400 Section 13 A/D Converter 13.4.2 Continuous Scan Mode In continuous scan mode, A/D conversion is to be performed sequentially on the specified channels (four channels maximum). 1. When the ADST bit in ADCR is set to 1 by software, MTU, MMT, or external trigger input, A/D conversion starts on the channel with the lowest number in the group (AN8, AN9, ..., AN11). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. Conversion of the first channel in the group starts again. 4. Steps 2 to 3 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters the idle state. 13.4.3 Single-Cycle Scan Mode In single-cycle scan mode, A/D conversion is to be performed once on the specified channels (four channels maximum). 1. When the ADST bit in ADCR is set to 1 by a software, MTU, MMT, or external trigger input, A/D conversion starts on the channel with the lowest number in the group (AN8, AN9, ..., AN11). 2. When A/D conversion for each channel is completed, the result is sequentially transferred to the A/D data register corresponding to each channel. 3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. 4. After A/D conversion ends, the ADST bit is automatically cleared to 0 and the A/D converter enters the idle state. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters the idle state. Rev. 4.00 Dec 05, 2005 page 378 of 564 REJ09B0270-0400 Section 13 A/D Converter 13.4.4 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit for each module. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit in ADCR is set to 1, then starts conversion. Figure 13.2 shows the A/D conversion timing. Table 13.3 shows the A/D conversion time. As indicated in figure 13.2, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCR. The total conversion time therefore varies within the ranges indicated in table 13.3. In scan mode, the values given in table 13.3 apply to the first conversion time. The values given in table 13.4 apply to the second and subsequent conversions. A/D conversion time (tCONV) A/D conversion start Analog input delay time(tD) sampling time(tSPL) Write cycle A/D synchronization time (Up to (3 states) 59 states) P Address Internal write signal ADST write timing Analog input sampling signal A/D converter Idle state Sample-and-hold A/D conversion ADF End of A/D conversion Figure 13.2 A/D Conversion Timing Rev. 4.00 Dec 05, 2005 page 379 of 564 REJ09B0270-0400 Section 13 A/D Converter Table 13.3 A/D Conversion Time (Single Mode) CKS1 = 0 CKS0 = 0 Item A/D conversion start delay time Input sampling time A/D conversion time Symbol tD tSPL tCONV Min 31 Typ 256 Max 62 1055 Min 15 515 CKS0 = 1 Typ 128 Max 30 530 Min 7 259 CKS0 = 0 Typ 64 Max 14 266 Min 3 131 CKS1 = 1 CKS0 = 1 Typ 32 Max 6 134 1024 Note: All values represent the number of states for P. Table 13.4 A/D Conversion Time (Scan Mode) CKS1 0 CKS0 0 1 1 0 1 Conversion Time (State) 1024 (Fixed) 512 (Fixed) 256 (Fixed) 128 (Fixed) 13.4.5 A/D Converter Activation by MTU or MMT The A/D converter can be independently activated by an A/D conversion request from the interval timer of the MTU or MMT. To activate the A/D converter by the MTU or MMT, set the A/D trigger select register (ADTSR). After this register setting has been made, the ADST bit in ADCR is automatically set to 1 when an A/D conversion request from the interval timer of the MTU or MMT occurs. The timing from setting of the ADST bit until the start of A/D conversion is the same as when 1 is written to the ADST bit by software. 13.4.6 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS0 and TRGS1 bits are set to 00 or 01 in ADTSR, external trigger input is enabled at the ADTRG pin. A falling edge of the ADTRG pin sets the ADST bit to 1 in ADCR, starting A/D conversion. Other operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 13.3 shows the timing. Rev. 4.00 Dec 05, 2005 page 380 of 564 REJ09B0270-0400 Section 13 A/D Converter CK ADTRG External trigger signal ADST A/D conversion Figure 13.3 External Trigger Input Timing 13.5 Interrupt Sources and DTC Transfer Requests The A/D converter generates an A/D conversion end interrupt (ADI) upon the completion of A/D conversion. ADI interrupt requests are enabled when the ADIE bit is set to 1 while the ADF bit in ADCSR is set to 1 after A/D conversion is completed. The data transfer controller (DTC) can be activated by an ADI interrupt. Having the converted data read by the DTC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. The A/D converter can generate an A/D conversion end interrupt request. The ADI interrupt can be enabled by setting the ADIE bit in the A/D control/status register (ADCSR) to 1, or disabled by clearing the ADIE bit to 0. The DTC can be activated by an ADI interrupt. In this case an interrupt request is not sent to the CPU. When the DTC is activated by an ADI interrupt, the ADF bit in ADCSR is automatically cleared when data is transferred by the DTC. Table 13.5 A/D Converter Interrupt Source Name ADI Interrupt Source A/D conversion completed Interrupt Source Flag ADF DTC Activation Possible Rev. 4.00 Dec 05, 2005 page 381 of 564 REJ09B0270-0400 Section 13 A/D Converter 13.6 Definitions of A/D Conversion Accuracy This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 13.4). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 13.5). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 13.5). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between zero voltage and fullscale voltage. Does not include offset error, full-scale error, or quantization error (see figure 13.5). * Absolute accuracy The deviation between the digital value and the analog input value. Includes offset error, fullscale error, quantization error, and nonlinearity error. Rev. 4.00 Dec 05, 2005 page 382 of 564 REJ09B0270-0400 Section 13 A/D Converter Digital output 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 13.4 Definitions of A/D Conversion Accuracy Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 13.5 Definitions of A/D Conversion Accuracy Rev. 4.00 Dec 05, 2005 page 383 of 564 REJ09B0270-0400 Section 13 A/D Converter 13.7 13.7.1 Usage Notes Module Standby Mode Setting Operation of the A/D converter can be disabled or enabled using the module standby control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 21, Power-Down Modes. 13.7.2 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 1 k or less (20 MHz to 25 MHz), or 3 k or less (20 MHz or Less). This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 1 k or 3 k, charging may be insufficient and it may not be possible to guarantee A/D conversion accuracy. However, for A/D conversion in single mode with a large capacitance provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 13.6). When converting a high-speed analog signal or converting in scan mode, a low-impedance buffer should be inserted. 13.7.3 Influences on Absolute Accuracy Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not interfere in the accuracy by the printed circuit digital signals on the mounting board (i.e, acting as antennas). Sensor output impedance of up to 3 k or up to 1 k Sensor input Low-pass filter C to 0.1 F This LSI A/D converter equivalent circuit 10 k Cin = 15 pF 20 pF Figure 13.6 Example of Analog Input Circuit Rev. 4.00 Dec 05, 2005 page 384 of 564 REJ09B0270-0400 Section 13 A/D Converter 13.7.4 Range of Analog Power Supply and Other Pin Settings If the conditions below are not met, the reliability of the device may be adversely affected. * Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss VAN AVcc. * Relationship between AVcc, AVss and Vcc, Vss Set AVss = Vss for the relationship between AVcc, AVss and Vcc, Vss. If the A/D converter is not used, the AVcc and AVss pins must not be left open. 13.7.5 Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN8 to AN19), and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable ground (Vss) on the board. 13.7.6 Notes on Noise Countermeasures A protection circuit should be connected in order to prevent damage due to abnormal voltage, such as an excessive surge at the analog input pins (AN8 to AN19), between AVcc and AVss, as shown in figure 13.7. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to AN8 to AN19 must be connected to AVss. If a filter capacitor is connected, the input currents at the analog input pins (AN8 to AN19) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding circuit constants. Rev. 4.00 Dec 05, 2005 page 385 of 564 REJ09B0270-0400 Section 13 A/D Converter AVCC Rin*2 *1 0.1 F 100 AN8 to AN19 AVSS Notes: Values are reference values. 1. 10 F 0.01 F 2. Rin: Input impedance Figure 13.7 Example of Analog Input Protection Circuit Table 13.6 Analog Pin Specifications Item Analog input capacitance Permissible signal source impedance Min Max 20 3 1 Unit pF k k 20 MHz 20 to 25 MHz Measurement conditions 10 k AN8 to AN19 To A/D converter 20 pF Note: Values are reference values. Figure 13.8 Analog Input Pin Equivalent Circuit Rev. 4.00 Dec 05, 2005 page 386 of 564 REJ09B0270-0400 Section 14 Compare Match Timer (CMT) Section 14 Compare Match Timer (CMT) This LSI has an on-chip compare match timer (CMT) comprising two 16-bit timer channels. The CMT has 16-bit counters and can generate interrupts at set intervals. 14.1 Features The CMT has the following features: * Four types of counter input clock can be selected One of four internal clocks (P/8, P/32, P/128, P/512) can be selected independently for each channel. * Interrupt sources A compare match interrupt can be requested independently for each channel. * Module standby mode can be set Figure 14.1 shows a block diagram of the CMT. P/32 P/512 P/8 P/128 P/32 P/512 P/8 P/128 CMI0 CMI1 Control circuit Clock selection Control circuit Clock selection Comparator CMCOR0 CMCSR0 CMCOR1 CMCSR1 CMCNT0 Comparator CMCNT1 CMSTR Module bus CMT Legend: CMSTR: CMCSR: CMCOR: CMCNT: CMI: Bus interface Internal bus Compare match timer start register Compare match timer control/status register Compare match timer constant register Compare match timer counter Compare match interrupt Figure 14.1 CMT Block Diagram TIMCMT0A_000020010100 Rev. 4.00 Dec 05, 2005 page 387 of 564 REJ09B0270-0400 Section 14 Compare Match Timer (CMT) 14.2 Register Descriptions The CMT has the following registers for each channel. For details on register addresses and register states during each processing, refer to appendix A, Internal I/O Register. * Compare Match Timer Start Register (CMSTR) * Compare Match Timer Control/Status Register_0 (CMCSR_0) * Compare Match Timer Counter_0 (CMCNT_0) * Compare Match Timer Constant Register_0 (CMCOR_0) * Compare Match Timer Control/Status Register_1 (CMCSR_1) * Compare Match Timer Counter_1 (CMCNT_1) * Compare Match Timer Constant Register_1 (CMCOR_1) 14.2.1 Compare Match Timer Start Register (CMSTR) The compare match timer start register (CMSTR) is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1 counters (CMCNT). Bit 15 to 2 1 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. STR1 0 R/W Count Start 1 This bit selects whether to operate or halt compare match timer counter_1. 0: CMCNT_1 count operation halted 1: CMCNT_1 count operation 0 STR0 0 R/W Count Start 0 This bit selects whether to operate or halt compare match timer counter_0. 0: CMCNT_0 count operation halted 1: CMCNT_0 count operation Rev. 4.00 Dec 05, 2005 page 388 of 564 REJ09B0270-0400 Section 14 Compare Match Timer (CMT) 14.2.2 Compare Match Timer Control/Status Register_0 and 1 (CMCSR_0, CMCSR_1) The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable status of interrupts, and establishes the clock used for incrementation. Bit 15 to 8 7 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. CMF 0 R/(W)* Compare Match Flag This flag indicates whether or not the CMCNT and CMCOR values have matched. 0: CMCNT and CMCOR values have not matched 1: CMCNT and CMCOR values have matched [Clearing conditions] * * Write 0 to CMF after reading 1 from it When the DTC is activated by an CMI interrupt and data is transferred with the DISEL bit in DTMR of DTC = 0 6 CMIE 0 R/W Compare Match Interrupt Enable This bit selects whether to enable or disable a compare match interrupt (CMI) when the CMCNT and CMCOR values have matched (CMF = 1). 0: Compare match interrupt (CMI) disabled 1: Compare match interrupt (CMI) enabled 5 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00 Dec 05, 2005 page 389 of 564 REJ09B0270-0400 Section 14 Compare Match Timer (CMT) Initial Value 0 0 Bit 1 0 Bit Name CKS1 CKS0 R/W R/W R/W Description These bits select the clock input to CMCNT among the four internal clocks obtained by dividing the peripheral clock (P). When the STR bit of CMSTR is set to 1, CMCNT begins incrementing with the clock selected by CKS1 and CKS0. 00: P/8 01: P/32 10: P/128 11: P/512 Note: * Only 0 can be written, for flag clearing. 14.2.3 Compare Match Timer Counter_0 and 1 (CMCNT_0, CMCNT_1) The compare match timer counter (CMCNT) is a 16-bit register used as an up-counter for generating interrupt requests. The initial value is H'0000. 14.2.4 Compare Match Timer Constant Register_0 and 1 (CMCOR_0, CMCOR_1) The compare match timer constant register (CMCOR) is a 16-bit register that sets the period for compare match with CMCNT. The initial value is H'FFFF. Rev. 4.00 Dec 05, 2005 page 390 of 564 REJ09B0270-0400 Section 14 Compare Match Timer (CMT) 14.3 14.3.1 Operation Cyclic Count Operation When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR bit of CMSTR is set to 1, CMCNT begins incrementing with the selected clock. When the CMCNT counter value matches that of the compare match constant register (CMCOR), the CMCNT counter is cleared to H'0000 and the CMF flag of the CMCSR register is set to 1. If the CMIE bit of the CMCSR register is set to 1 at this time, a compare match interrupt (CMI) is requested. The CMCNT counter begins counting up again from H'0000. Figure 14.2 shows the compare match counter operation. CMCNT value Counter cleared by CMCOR compare match CMCOR H'0000 Time Figure 14.2 Counter Operation 14.3.2 CMCNT Count Timing One of four internal clocks (P/8, P/32, P/128, P/512) obtained by dividing the peripheral clock (P) can be selected by the CKS1 and CKS0 bits of CMCSR. Figure 14.3 shows the timing. P Internal clock CMCNT input clock CMCNT N-1 N N+1 Figure 14.3 Count Timing Rev. 4.00 Dec 05, 2005 page 391 of 564 REJ09B0270-0400 Section 14 Compare Match Timer (CMT) 14.4 14.4.1 Interrupts Interrupt Sources The CMT has a compare match interrupt for each channel, with independent vector addresses allocated to each of them. The corresponding interrupt request is output when interrupt request flag CMF is set to 1 and interrupt enable bit CMIE has also been set to 1. When activating CPU interrupts by interrupt request, the priority between the channels can be changed by means of interrupt controller settings. See section 6, Interrupt Controller (INTC), for details. The data transfer controller (DTC) can be activated by an interrupt request. In this case, the priority between channels is fixed. See section 8, Data Transfer Controller (DTC), for details. 14.4.2 Compare Match Flag Set Timing The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the CMCOR register and the CMCNT counter match. The compare match signal is generated upon the final state of the match (timing at which the CMCNT counter matching count value is updated). Consequently, after the CMCOR register and the CMCNT counter match, a compare match signal will not be generated until a CMCNT counter input clock occurs. Figure 14.4 shows the CMF bit set timing. P CMCNT input clock CMCNT CMCOR Compare match signal CMF CMI N N 0 Figure 14.4 CMF Set Timing Rev. 4.00 Dec 05, 2005 page 392 of 564 REJ09B0270-0400 Section 14 Compare Match Timer (CMT) 14.4.3 Compare Match Flag Clear Timing The CMF bit of the CMCSR register is cleared by writing 0 to it after reading 1 or the clearing signal after the DTC transfer. Figure 14.5 shows the timing when the CMF bit is cleared by the CPU. CMCSR write cycle T1 T2 P CMF Figure 14.5 Timing of CMF Clear by the CPU 14.5 14.5.1 Usage Notes Contention between CMCNT Write and Compare Match If a compare match signal is generated during the T2 state of the CMCNT counter write cycle, the CMCNT counter clear has priority, so the write to the CMCNT counter is not performed. Figure 14.6 shows the timing. CMCNT write cycle T1 T2 P Address Internal write signal Compare match signal CMCNT N H' 0000 CMCNT Figure 14.6 CMCNT Write and Compare Match Contention Rev. 4.00 Dec 05, 2005 page 393 of 564 REJ09B0270-0400 Section 14 Compare Match Timer (CMT) 14.5.2 Contention between CMCNT Word Write and Incrementation If an increment occurs during the T2 state of the CMCNT counter word write cycle, the counter write has priority, so no increment occurs. Figure 14.7 shows the timing. CMCNT write cycle T1 T2 P Address Internal write signal CMCNT input clock CMCNT N M CMCNT write data CMCNT Figure 14.7 CMCNT Word Write and Increment Contention Rev. 4.00 Dec 05, 2005 page 394 of 564 REJ09B0270-0400 Section 14 Compare Match Timer (CMT) 14.5.3 Contention between CMCNT Byte Write and Incrementation If an increment occurs during the T2 state of the CMCNT byte write cycle, the counter write has priority, so no increment of the write data results on the side on which the write was performed. The byte data on the side on which writing was not performed is also not incremented, so the contents are those before the write. Figure 14.8 shows the timing when an increment occurs during the T2 state of the CMCNTH write cycle. CMCNT write cycle T1 T2 P Address Internal write signal CMCNT input clock CMCNTH N M CMCNTH write data CMCNTL X X CMCNTH Figure 14.8 CMCNT Byte Write and Increment Contention Rev. 4.00 Dec 05, 2005 page 395 of 564 REJ09B0270-0400 Section 14 Compare Match Timer (CMT) Rev. 4.00 Dec 05, 2005 page 396 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) Section 15 Motor Management Timer (MMT) Motor Management Timer (MMT) can output 6-phase PWM waveforms with non-overlap times. Figure 15.1 shows a block diagram of the MMT. 15.1 Features * Triangular wave comparison type 6-phase PWM waveform output with non-overlap times * Non-overlap times generated by timer dead time counters * Toggle output synchronized with PWM period * Counter clearing on an external signal * Data transfer by DTC activation * Generation of a trigger for the start of conversion by the A/D converter is available. * Output-off functions * PWM output halted by external signal * PWM output halted when oscillation stops * Module standby mode can be set PWMMMT1A_010020010900 Rev. 4.00 Dec 05, 2005 page 397 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) TPDR compare match interrupt 2Td compare match interrupt TPBR MMT_TDDR x2 Comparators TDCNT0 TPDR Comparators PCIO +2Td Control circuit P to P/1024 PUOA PUOB PVOA PVOB PWOA PWOB A/D start-conversion request signal MMT_TCNT Magnitude comparators TGRWU TGRWD MMT_TMDR TCNR TGRUU TGRUD TGRVU TGRVD +Td +Td +2Td +2Td +2Td +Td TGRW TGRU TGRV TBRU TBRV TBRW MMT_TSR Legend: TGR: TBR: MMT_TDDR: TPDR: TPBR: Td: Timer general register Timer buffer register Timer dead time data register Timer period data register Timer period buffer register Dead time MMT_TMDR: TCNR: MMT_TSR: MMT_TCNT: TDCNT: P: Timer mode register Timer control register Timer status register Timer counter Timer dead time counter Peripheral clock Figure 15.1 Block Diagram of MMT Rev. 4.00 Dec 05, 2005 page 398 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) 15.2 Input/Output Pins Table 15.1 shows the pin configuration of the MMT. Table 15.1 Pin Configuration Name PCIO I/O Input/Output Function Counter clear signal input when set as an input by PAIORL register: toggle output in synchronization with the PWM cycle when set as an output by PAIORL register. PWMU phase output (positive phase) PWMU phase output (negative phase) PWMV phase output (positive phase) PWMV phase output (negative phase) PWMW phase output (positive phase) PWMW phase output (negative phase) PUOA PUOB PVOA PVOB PWOA PWOB Output Output Output Output Output Output Rev. 4.00 Dec 05, 2005 page 399 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) 15.3 Register Descriptions The MMT has the following registers. For details on register addresses and the register states during each processing, refer to appendix A, Internal I/O Register. * Timer mode register (MMT_TMDR*) * Timer control register (TCNR) * Timer status register (MMT_TSR*) * Timer counter (MMT_TCNT*) * Timer buffer register U (TBRU) * Timer buffer register V (TBRV) * Timer buffer register W (TBRW) * Timer general register UU (TGRUU) * Timer general register VU (TGRVU) * Timer general register WU (TGRWU) * Timer general register U (TGRU) * Timer general register V (TGRV) * Timer general register W (TGRW) * Timer general register UD (TGRUD) * Timer general register VD (TGRVD) * Timer general register WD (TGRWD) * Timer dead time counter 0 (TDCNT0) * Timer dead time counter 1 (TDCNT1) * Timer dead time counter 2 (TDCNT2) * Timer dead time counter 3 (TDCNT3) * Timer dead time counter 4 (TDCNT4) * Timer dead time counter 5 (TDCNT5) * Timer dead time data register (MMT_TDDR*) * Timer period buffer register (TPBR) * Timer period data register (TPDR) Note: * In this section, the names of these registers are further abbreviated to TMDR, TSR, TCNT, and TDDR hereafter. Rev. 4.00 Dec 05, 2005 page 400 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) 15.3.1 Timer Mode Register (MMT_TMDR) The timer mode register (MMT_TMDR) sets the operating mode and selects the PWM output level. In this section, the name of this register is abbreviated to TMDR hereafter. Bit 7 Bit Name Initial Value 0 R/W R Description Reserved These bits are always read as 0 and should only be written with 0. 6 5 4 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select 2 to 0 Selects the clock input to MMT. 000: P 001: P/4 010: P/16 011: P/64 100: P/256 101: P/1024 11x: Setting prohibited. Note: x "don't care". 3 OLSN 0 R/W Output Level Select N Selects the negative phase output level in the operating modes. 0: Active level is low 1: Active level is high 2 OLSP 0 R/W Output Level Select P Selects the positive phase output level in the operating modes. 0: Active level is low 1: Active level is high Rev. 4.00 Dec 05, 2005 page 401 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) Initial Value 0 0 Bit 1 0 Bit Name MD1 MD0 R/W R/W R/W Description Mode 0 to 3 These bits set the timer operating mode. 00: Operation halted 01: Operating mode 1 (Transfer at TCNT = TPDR) 10: Operating mode 2 (Transfer at TCNT = TDDR x 2) 11: Operating mode 3 (Transfer at TCNT = TPDR or TCNT = TDDR x 2) 15.3.2 Timer Control Register (TCNR) The timer control register (TCNR) controls the enabling or disabling of interrupt requests, selects the enabling or disabling of register access, and selects counter operation or halting. Bit 7 Bit Name TTGE Initial Value 0 R/W R/W Description A/D Start-Conversion request Enable Enables or disables the generation of A/D startconversion requests when the TGFN or TGFM bit of the timer status register (TSR) is set. 0: Disables request 1: Enables request 6 CST 0 R/W Timer Counter Start Selects operation or halting of the timer counter (TCNT) and timer dead time counter (TDCNT). 0: TCNT and TDCNT operation is halted 1: TCNT and TDCNT perform count operations 5 RPRO 0 R/W Register Protects Enables or disables the reading of registers other than TSR, and enables or disables the writing to registers other than TBRU to TBRW, TPBR, and TSR. Writes to TCNR itself are also disabled. Note that reset input is necessary in order to write to these registers again. 0: Register access enabled 1: Register access disabled Rev. 4.00 Dec 05, 2005 page 402 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) Initial Value All 0 Bit 4 to 2 Bit Name R/W R Description Reserved These bits are always read as 0. Only 0 should be written to these bits. 1 TGIEN 0 R/W TGR Interrupt Enable N Enables or disables interrupt requests by the TGFN bit when TGFN is set to 1 in the TSR register. 0: Interrupt requests by TGFN bit disabled 1: Interrupt requests by TGFN bit enabled 0 TGIEM 0 R/W TGR Interrupt Enable M Enables or disables interrupt requests by the TGFM bit when TGFM is set to 1 in the TSR register. 0: Interrupt requests by TGFM bit disabled 1: Interrupt requests by TGFM bit enabled Rev. 4.00 Dec 05, 2005 page 403 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) 15.3.3 Timer Status Register (MMT_TSR) The timer status register (MMT_TSR) holds status flags. (In this section, the name of this register is abbreviated to TSR hereafter.) Bit 7 Bit Name TCFD Initial Value 1 R/W R Description Count Direction Flag Status flag that indicates the count direction of the TCNT counter. 0: TCNT counts down 1: TCNT counts up 6 to 2 All 0 R Reserved These bits are always read as 0 and should only be written with 0. 1 TGFN 0 R/(W)* Output Compare Flag N Status flag that indicates a compare match between TCNT and 2Td (Td: TDDR value). [Setting condition] * * 0 TGFM 0 R/(W)* When TCNT = 2Td When 0 is written to TGFN after reading TGFN = 1 [Clearing condition] Output Compare Flag M Status flag that indicates a compare match between TCNT and the TPDR register. [Setting condition] * * Note: * When TCNT = TPDR When 0 is written to TGFM after reading TGFM = 1 [Clearing condition] Can only be written with 0 for flag clearing. Rev. 4.00 Dec 05, 2005 page 404 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) 15.3.4 Timer Counter (MMT_TCNT) The timer counter (MMT_TCNT) is a 16-bit counter. The initial value is H'0000. Only 16-bit access can be used on MMT_TCNT; 8-bit access is not possible. (In this section, the name of this register is abbreviated to TCNT hereafter.) 15.3.5 Timer Buffer Registers (TBR) The timer buffer registers (TBR) function as 16-bit buffer registers. The MMT has three TBR registers; TBRU, TBRV, and TBRW, each of which has two addresses; a buffer operation address (shown first) and a free operation address (shown second). A value written to the buffer operation address is transferred to the corresponding TGR at the timing set in bits MD1 and MD0 in the timer mode register (TMDR). A value set in the free operation address is transferred to the corresponding TGR immediately. The initial value of TBR is H'FFFF. Only 16-bit access can be used on the TBR registers; 8-bit access is not possible. 15.3.6 Timer General Registers (TGR) The timer general registers (TGR) function as 16-bit compare registers. The MMT has nine TGR registers, that are compared with the TCNT counter in the operating modes. The initial value of TGR is H'FFFF. Only 16-bit access can be used on the TGR registers; 8-bit access is not possible. 15.3.7 Timer Dead Time Counters (TDCNT) The timer dead time counters (TDCNT) are 16-bit read-only counters. The initial value of TDCNT is H'0000. Only 16-bit access can be used on the TDCNT counters; 8-bit access is not possible. 15.3.8 Timer Dead Time Data Register (MMT_TDDR) The timer dead time data register (MMT_TDDR) is a 16-bit register that sets the positive phase and negative phase non-overlap time (dead time). The initial value of MMT_TDDR is H'FFFF. Only 16-bit access can be used on MMT_TDDR; 8-bit access is not possible. (In this section, the name of this register is further abbreviated to TDDR hereafter.) Rev. 4.00 Dec 05, 2005 page 405 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) 15.3.9 Timer Period Buffer Register (TPBR) The timer period buffer register (TPBR) is a 16-bit register that functions as a buffer register for the TPDR register. A value of 1/2 the PWM carrier period should be set as the TPBR value. The TPBR value is transferred to the TPDR register at the transfer timing set in the TMDR register. The initial value of TPBR is H'FFFF. Only 16-bit access can be used on TPBR; 8-bit access is not possible. 15.3.10 Timer Period Data Register (TPDR) The timer period data register (TPDR) functions as a 16-bit compare register. In the operating modes, the TPDR register value is constantly compared with the TCNT counter value, and when they match the TCNT counter changes its count direction from up to down. The initial value of TPDR is H'FFFF. Only 16-bit access can be used on TPDR; 8-bit access is not possible. 15.4 Operation When the operating mode is selected, a 3-phase PWM waveform is output with a non-overlap relationship between the positive and negative phases. The PUOA, PUOB, PVOA, PVOB, PWOA, and PWOB pins are PWM output pins, the PCIO pin (when set to output) functions as a toggle output synchronized with the PWM waveform, and the PCI0 pin (when set to input) functions as the counter clear signal input. The TCNT counter performs up- and down-count operations, whereas the TDCNT counters perform up-count operations. Rev. 4.00 Dec 05, 2005 page 406 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) 15.4.1 Sample Setting Procedure An example of the operating mode setting procedure is shown in figure 15.2. Clear the CST bit to 0 in the timer control register (TCNR) to halt timer counter operation. Make the operating mode setting while TCNT is halted. Set 2Td (Td: dead time) in TCNT. Halt count operation Set TCNT Set dead time carrier period Set dead time Td in the dead time data register (TDDR), set 1/2 the carrier period in the timer period buffer register (TPBR), and set {TPBR value + 2Td} in the timer period data register (TPDR). Set the output PWM duty cycle {PWM duty cycle initial value - Td} in the free operation addresses of the buffer registers (TBRU, TBRV, TBRW). Set TBR Set PWM output level Set the PWM output level with bits OLSN and OLSP in the timer mode register (TMDR). Set operating mode Set the operating mode in the timer mode register (TMDR). The PUOA, PUOB, PVOA, PVOB, PWOA, and PWOB pins are output pins. Set the external pin functions with the pin function controller (PFC). Set external pin functions Start count operation Set the CST bit to 1 in TCNR to start the count operation. Figure 15.2 Sample Operating Mode Setting Procedure Rev. 4.00 Dec 05, 2005 page 407 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) Count Operation: Set 2Td (Td: value set in TDDR) as the initial value of the TCNT counter when CST bit in TCNR is set to 0. When the CST bit is set to 1, TCNT counts up to {value set in TPBR + 2Td}, and then starts counting down. When TCNT reaches 2Td, it starts counting up again, and continues in this way. TCNT is constantly compared with TGRU, TGRV, and TGRW. In addition, it is compared with TGRUU, TGRVU, TGRWU, and TPDR when counting up, and with TGRUD, TGRVD, TGRWD, and 2Td when counting down. TDCNT0 to TDCNT5 are read-only counters. It is not necessary to set their initial values. TDCNT0, TDCNT2, and TDCNT4 start counting up at the falling edge of a positive phase compare match output when TCNT is counting down. When they become equal to TDDR they are cleared to 0 and halt. TDCNT1, TDCNT3, and TDCNT5 start counting up at the falling edge of a negative phase compare match output when TCNT is counting up. When they match TDDR they are cleared to 0 and halt. TDCNT0 to TDCNT5 are compared with TDDR only while a count operation is in progress. No count operation is performed when the TDDR value is 0. Figure 15.3 shows an example of the TCNT count operation. H'FFFF 2Td TPDR TCNT TGRUU TGRU TGRUD Td Td 1/2 period (TPBR) 2Td H'0000 2Td Td Figure 15.3 Example of TCNT Count Operation Rev. 4.00 Dec 05, 2005 page 408 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) Register Operation: In the operating modes, four buffer registers and ten compare registers are used. The registers that are constantly compared with the TCNT counter are TGRU, TGRV, and TGRW. In addition, TGRUU, TGRVU, TGRWU, and TPDR are compared with TCNT when TCNT is counting up, and TGRUD, TGRVD, TGRWD are compared with TCNT when TCNT is counting down. The buffer register for TPDR is TPBR; the buffer register for TGRUU, TGRU, and TGRUD is TBRU; the buffer register for TGRVU, TGRV, and TGRVD is TBRV; and the buffer register for TGRWU, TGRW, and TGRWD is TBRW. To change compare register data, the new data should be written to the corresponding buffer register. The buffer registers can be read and written to at all times. Data written to the buffer operation addresses for TPBR and TBRU to TBRW is transferred at the timing specified by bits MD1 and MD0 in the timer mode register (TMDR). Data written to the free operation addresses for TBRU to TBRW is transferred immediately. After data transfer is completed, the relationship between the compare registers and buffer registers is as follows: TGRU (TGRV, TGRW) value = TBRU (TBRV, TBRW) value + Td (Td: value set in TDDR) TGRUU (TGRVU, TGRWU) value = TBRU (TBRV, TBRW) value + 2Td TGRUD (TGRVD, TGRWD) value = TBRU (TBRV, TBRW) value TPDR value = TPBR value + 2Td The values of TBRU to TBRW should always be set in the range H'0000 to H'FFFF - 2Td, and the value of TPBR should always be set in the range H'0000 to H'FFFF - 4Td. Figure 15.4 shows examples of counter and register operations. Rev. 4.00 Dec 05, 2005 page 409 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) x2 + TGRUU TGRVU TGRWU (TBR + 2Td) Compared during up-count TDDR (Td) TBRU TBRV TBRW (TBR) + TGRU TGRV TGRW (TBR + Td) TCNT Constantly compared TGRUD TGRVD TGRWD (TBR) Compared during down-count (1/2 period + 2Td) TPBR (1/2 period) + TPDR Compared during up-count TCNT TDDR (Td) x2 (2Td) Compared during down-count Down-count compare match up-count Up-count compare match down-count TDDR (Td) Up-count compare match halt TDCNT Figure 15.4 Examples of Counter and Register Operations Initial Settings: In the operating modes, there are five registers that require initialization. Make the following register settings before setting the operating mode with bits MD1 and MD0 in the timer mode register (TMDR). Set the timer period buffer register (TPBR) to 1/2 the PWM carrier period, set dead time Td in the timer dead time data register (TDDR) (when outputting an ideal waveform, Td = H'0000), and set {TPBR value + 2Td} in the timer period data register (TPDR). Rev. 4.00 Dec 05, 2005 page 410 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) Set {PWM duty initial value - Td} in the free write operation addresses for TBRU to TBRW. The values of TBRU to TBRW should always be set in the range H'0000 to H'FFFF - 2Td, and the value of TPBR should always be set in the range H'0000 to H'FFFF - 4Td. PWM Output Active Level Setting: In the operating modes, the active level of PWM pulses is set with bits OLSN and OLSP in the timer mode register (TMDR). The output level can be set for the three positive phases and the three negative phases of 6-phase output. The operating mode must be exited before setting or changing the output level. Dead Time Setting: In the operating modes, PWM pulses are output with a non-overlap relationship between the positive and negative phases. This non-overlap time is known as the dead time. The non-overlap time is set in the timer dead time data register (TDDR). The dead time generation waveform is generated by comparing the value set in TDDR with the timer dead time counters (TDCNT) for each phase. The operating mode must be exited before changing the contents of TDDR. PWM Period Setting: In the operating modes, 1/2 the PWM pulse period is set in the TPBR register. The TPBR value should always be set in the range H'0000 to H'FFFF - 4Td. The value set in TPBR is transferred to TPDR at the timing selected with bits MD1 and MD0 in the timer mode register (TMDR). After the transfer, the value in TPDR is {TPBR value + 2Td}. The new PWM period is effective from the next period when data is updated at the TCNT counter crest, and from the same period when data is updated at the trough. Register Updating: In the operating modes, buffer registers are used to update compare register data. Update data can be written to a buffer register at all times. The buffer register value is transferred to the compare register at the timing set by bits MD1 and MD0 in the timer mode register (TMDR) (except in the case of a write to the free operation address for TBRU to TBRW, in which case the value is transferred to the corresponding compare register immediately). Initial Output in Operating Modes: The initial output in the operating modes is determined by the initial values of TBRU to TBRW. Table 15.2 shows the relationship between the initial value of TBRU to TBRW and the initial output. Rev. 4.00 Dec 05, 2005 page 411 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) Table 15.2 Initial Values of TBRU to TBRW and Initial Output Initial Output Initial Value of TBRU to TBRW TBR = H'0000 H'0000 < TBR Td Td < TBR H'FFFF - 2Td OLSP = 1, OLSN = 1 Positive phase: 1 Negative phase: 0 Positive phase: 0 Negative phase: 0 Positive phase: 0 Negative phase: 1 OLSP = 0, OLSN = 0 Positive phase: 0 Negative phase: 1 Positive phase: 1 Negative phase: 1 Positive phase: 1 Negative phase: 0 PWM Output Generation in Operating Modes: In the operating modes, a 3-phase PWM waveform is output with a non-overlap relationship between the positive and negative phases. This non-overlap time is called the dead time. The PWM waveform is generated from an output generation waveform generated by ANDing the compare output waveform with the dead time generation waveform. Waveform generation for one phase (the U-phase) is shown here. The V-phase and W-phase waveforms are generated in the same way. 1. Compare Output Waveform The compare output waveform is generated by comparing the values in the TCNT counter and the TGR registers. For compare output waveform U phase A (CMOUA), 0 is output if TGRUU > TCNT in the T1 interval (when TCNT is counting up), and 1 is output if TGRUU TCNT. In the T2 interval (when TCNT is counting down), 0 is output if TGRU > TCNT, and 1 is output if TGRU TCNT. For compare output waveform U phase B (CMOUB), 1 is output if TGRU > TCNT in the T1 interval, and 0 is output if TGRU TCNT. In the T2 interval, 1 is output if TGRUD > TCNT, and 0 is output if TGRUD TCNT. 2. Dead Time Generation Waveform For dead time generation waveform U phases A (DTGUA) and B (DTGUB), 1 is output as the initial value. TDCNT0 starts counting at the falling edge of CMOUA. DTGUA outputs 0 if TDCNT0 is counting, and 1 otherwise. TDCNT1 starts counting at the falling edge of CMOUB. DTGUB outputs 0 if TDCNT1 is counting, and 1 otherwise. Rev. 4.00 Dec 05, 2005 page 412 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) 3. Output Generation Waveform Output generation waveform U phase A (OGUA) is generated by ANDing CMOUA and DTGUB, and output generation waveform U phase B (OGUB) is generated by ANDing CMOUB and DTGUA. 4. PWM Waveform The PWM waveform is generated by converting the output generation waveform to the output level set in bits OLSN and OLSP in the timer mode register (TMDR). Figure 15.5 shows an example of PWM waveform generation (operating mode 3, OLSN = 1, OLSP = 1). When writing to free operation address TPDR 2Td Compare output waveform Dead time generation waveform Output generation waveform PWM waveform Figure 15.5 Example of PWM Waveform Generation 0% to 100% Duty Cycle Output: In the operating modes, PWM waveforms with any duty cycle from 0% to 100% can be output. The output PWM duty cycle is set using the buffer registers (TBRU to TBRW). 100% duty cycle output is performed when the buffer register (TBRU to TBRW) value is set to H'0000. The waveform in this case has positive phase in the 100% on state. 0% duty cycle output is performed when a value greater than the TPDR value is set as the buffer register (TBRU to TBRW) value. The waveform in this case has positive phase in the 100% off state. Rev. 4.00 Dec 05, 2005 page 413 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) External Counter Clear Function: In the operating modes, the TCNT counter can be cleared from an external source. When using the counter clearing function, port A I/O register L (PAIORL) should be used to set the PCIO pin as an input. On the falling edge of PCIO pin (when set to input), the TCNT counter is reset to 2Td (the initial setting). It then counts up until it reaches the value in TPDR, then starts counting down. When the count returns to 2Td, TCNT starts counting up again, and this sequence is repeated. Figure 15.6 shows the example for counter clearing. TPDR TCNT 2Td H'0000 PCIO (counter clear input) Figure 15.6 Example of TCNT Counter Clearing Toggle Output Synchronized with PWM Cycle: In the operating modes, output can be toggled synchronously with the PWM carrier cycle. When outputting the PWM cycle, the pin function controller (PFC) should be used to set the PCIO pin as an output(when set to output). An example of the toggle output waveform is shown in figure 15.7. PWM cycle output is toggled according to the TCNT count direction. The toggle output pin is PCIO (when set to output). PCIO outputs 1 when TCNT is counting up, and 0 when counting down. Rev. 4.00 Dec 05, 2005 page 414 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) TPDR TCNT 2Td H'0000 PCIO pin (toggle output) Figure 15.7 Example of Toggle Output Waveform Synchronized with PWM Cycle Settings for A/D Start-Conversion Requests: Requests to start A/D conversion can be set up to be issued when TCNT matches TPDR or 2Td. When the start requests are set up for issue when TCNT matches TPDR, A/D conversion will start at the center of the PWM pulse (the peak value of the TCNT counter). When the start requests are set up for issue when TCNT matches 2Td, A/D conversion will start on the edge of the PWM pulse (the minimum value of the TCNT counter). Requests to start A/D conversion is enabled by setting the bit TTGE in the timer control register (TCNR) to 1. Table 15.3 shows the relationship between A/D conversion start timing and operating mode. Table 15.3 Relationship between A/D Conversion Start Timing and Operating Mode Operating mode Operating mode 1 (transfer at peak) Operating mode 2 (transfer at bottom) Operating mode 3 (transfer at peak and valley) A/D conversion start timing A/D conversion start at bottom A/D conversion start at peak A/D conversion start at peak and bottom Rev. 4.00 Dec 05, 2005 page 415 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) 15.4.2 Output Protection Functions Operating mode output has the following protection functions: * Halting MMT output by external signal The 6-phase PWM output pins can be placed in the high-impedance state automatically by inputting a specified external signal. There are three external signal input pins. For details, see section 15.8, Port Output Enable (POE). * Halting MMT output when oscillation stops The 6-phase PWM output pins are placed in the high-impedance state automatically when stoppage of the clock input is detected. However, pin states are not guaranteed when the clock is restarted. 15.5 Interrupts When the TGFM (TGFN) flag is set to 1 in the timer status register (TSR) by a compare match between TCNT and the TPDR register (2Td), and if the TGIEM (TGIEN) bit setting in the timer control register (TCNR) is 1, an interrupt is requested. The interrupt request is cleared by clearing the TGF flag to 0. Table 15.4 MMT Interrupt Sources Name TGIMN TGINN Interrupt Source Compare match between TCNT and TPDR Compare match between TCNT and 2Td Interrupt Flag TGFM TGFN DTC Activation Yes Yes The on-chip DTC can be activated by a compare match between TCNT and TPDR or between TCNT and 2Td. The on-chip A/D converter can be activated when TCNT matches TPDR or 2Td. When the TGF flag in the timer status register (TSR) is set to 1 as a result of either match corresponding, a request to start A/D conversion is sent to the A/D converter. If the start-conversion trigger of the MMT is selected in the A/D converter at that time, A/D conversion starts up. Rev. 4.00 Dec 05, 2005 page 416 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) 15.6 15.6.1 Operation Timing Input/Output Timing TCNT and TDCNT Count Timing: Figure 15.8 shows the TCNT and TDCNT count timing. P TCNT, TDCNT N-3 N-2 N-1 N N+1 N+2 N+3 N+4 Figure 15.8 Count Timing TCNT Counter Clearing Timing: Figure 15.9 shows the timing of TCNT counter clearing by an external signal. P Counter clear signal TCNT N-3 N-2 N-1 N N+1 2Td 2Td + 1 2Td + 2 TDDR Td Figure 15.9 TCNT Counter Clearing Timing Rev. 4.00 Dec 05, 2005 page 417 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) TDCNT Operation Timing: Figure 15.10 shows the TDCNT operation timing. P CMO TDCNT H'0000 H'0001 . . . . Td - 1 Td H'0000 TDDR Compare match signal DTG TDCNT clear signal Td Notes: CMO: Compare match flag of TGR + TDDR and TCNT DTG: Operation signal of TDCNT Figure 15.10 TDCNT Operation Timing Rev. 4.00 Dec 05, 2005 page 418 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) Buffer Operation Timing: Figure 15.11 shows the compare match buffer operation timing. P Compare match signal TCNT N-1 N N-1 .... 2Td + 1 2Td 2Td + 1 2Td + 2 TPDR M0 + 2Td M1 + 2Td M2 + 2Td TPBR M0 M1 M2 TDDR TGRUU, TGRVU, TGRWU TGRU, TGRV, TGRW TGRUD, TGRVD, TGRWD TBRU, TBRV, TBRW L0 Td L0 + 2Td L1 + 2Td L2 + 2Td L0 + Td L0 L1 + Td L1 L2 + Td L2 L1 L2 Figure 15.11 Buffer Operation Timing Rev. 4.00 Dec 05, 2005 page 419 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) 15.6.2 Interrupt Signal Timing Timing of TGF Flag Setting by Compare Match: Figure 15.12 shows the timing of setting of the TGF flag in the timer status register (TSR) on a compare match between TCNT and TPDR, and the timing of the TGI interrupt request signal. The timing is the same for a compare match between TCNT and 2Td. P TCNT N-3 N-2 N-1 N N+1 N+2 N+3 N+4 TPDR Compare match signal N TGF flag TGI interrupt Figure 15.12 TGI Interrupt Timing Rev. 4.00 Dec 05, 2005 page 420 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) Status Flag Clearing Timing: A status flag is cleared when the CPU reads 1 from the flag, then 0 is written to it. When the DTC controller is activated, the flag is cleared automatically. Figure 15.13 shows the timing of status flag clearing by the CPU, and figure 15.14 shows the timing of status flag clearing by the DTC. TSR write cycle T1 T2 P Address TSR address Write signal Status flag Interrupt request signal Figure 15.13 Timing of Status Flag Clearing by CPU DTC read cycle T1 T2 P Source address DTC write cycle T1 T2 Address Destination address Status flag Interrupt request signal Figure 15.14 Timing of Status Flag Clearing by DTC Controller Rev. 4.00 Dec 05, 2005 page 421 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) 15.7 15.7.1 Usage Notes Module Standby Mode Setting MMT operation can be disabled or enabled using the module standby control register. The initial setting is for MMT operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 21, Power-Down Modes. 15.7.2 Notes for MMT Operation Note that the kinds of operation and contention described below occur during MMT operation. Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T2 state of a buffer register (TBRU to TBRW, or TPBR) write cycle, data is transferred from the buffer register to the compare register (TGR or TPDR) by a buffer operation. The data transferred is the buffer register write data. Figure 15.15 shows the timing in this case. Buffer register write cycle T1 P Address Buffer register address T2 Write signal Compare match signal Interrupt request signal Buffer register write data Buffer register N M Compare register M Figure 15.15 Contention between Buffer Register Write and Compare Match Rev. 4.00 Dec 05, 2005 page 422 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) Contention between Compare Register Write and Compare Match: If a compare match occurs in the T2 state of a compare register (TGR or TPDR) write cycle, the compare register write is not performed, and data is transferred from the buffer register (TBRU, TBRV, TBRW, or TPBR) to the compare register by a buffer operation. Figure 15.16 shows the timing in this case. Compare register write cycle T1 P Address Compare register address T2 Write signal Compare match signal Interrupt request signal Buffer register N Compare register N Figure 15.16 Contention between Compare Register Write and Compare Match Rev. 4.00 Dec 05, 2005 page 423 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) Pay Attention to the Notices Below, When a Value is Written into the Timer General Register U (TGRU), Timer General Register V (TGRV), Timer General Register W (TGRW), and in Case of Written into Free Operation Address (*): * In case of counting up: Do not write a value {Previous value of TGRU + Td} into TGRU. * In case of counting down: Do not write a value {Previous value of TGRU - Td} into TGRU. In the same manner to TGRV and TGRW. When a value {Previous value of TGRU + Td} is written (in case of counting down {Previous value of TGRU - Td}), the output of PUOA/PUOB, PVOA/PVOB, PWOA/PWOB (corresponding to U, V, W phase) may not be output for 1 cycle. Figure 15.17 shows the error case. When writing into the buffer operation address, these notes are not relevant. Note: * When addresses, H'FFFF8A1C, H'FFFF8A2C, H'FFFF8A3C are used as register address for TBRU, TBRV, TBRW, respectively. TGRU PreviousTGRU Td PreviousTGRU TGRU Td 2Td 2Td Count-up Count down Figure 15.17 Writing into Timer General Registers (When One Cycle is Not Output) Writing Operation into Timer Period Data Register (TPDR) and Timer Dead Time Data Register (TDDR) When MMT is Operating: * Do not revise TPDR register when MMT is operating. Always use a buffer-write operation through TPBR register. * Do not revise TDDR register once an operation of MMT is invoked. When TDDR is revised, a wave may not be output for as much as 1 cycle (full count period of 16 bits in TDCNT), because a value cannot be written into TDCNT, which is compared to a value set in TDDR. Rev. 4.00 Dec 05, 2005 page 424 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) Notes on Halting TCNT Counter Operation: If TCNT counter operation is halted, a PCM waveform may be output with dead time (non-overlap time) shorter than the value set in the timer dead time register (MMT_TDDR) or no dead time at all (value of 0). To prevent this, use one of the following methods. (a) Set the CST bit in the timer control register (TCNR) to 1 and do not clear it to 0 after MMT counter operation starts. If the CST bit is cleared to 0, do not set it to 1 again. (b) When setting, clearing, and then resetting the CST bit, use the following procedure for clearing and then resetting. (1) Use the pin function controller (PFC) to set the PWM output pin as a general input port. (2) Set the free operation addresses for all the buffer registers (TBRU, TBRV, and TBRW) to H'0000. (3) After the specified dead time duration has elapsed, set TCNR to H'00 and clear the CST bit to 0. (4) Once again, set the CST bit to 1. (c) When setting, clearing, and then resetting the CST bit, use the following procedure for clearing and then resetting. (1) Clear the CST bit in TCNR to 0 to halt counter operation. (2) Use the pin function controller to set the PWM output pin as a general input port. (3) Clear the MSTP14 bit in module standby control register 2 (MSTCR2) to 0 to transition to module standby mode, and initialize the internal status of MMT. (4) Immediately set the MSTP14 bit to 1 to transition back from module standby mode. Reinitialize MMT and the pin. (5) Set the CST bit in TCNR to 1 to restart counter operation. Rev. 4.00 Dec 05, 2005 page 425 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) 15.8 Port Output Enable (POE) The port output enable (POE) circuit enables the MMT's output pins (POUA, POUB, POVA, POVB, POWA, and POWB) to be placed in the high-impedance state by varying the input to pins POE4 to POE6. An interrupt can also be requested at the same time. In addition, the MMT's output pins will also enter the high-impedance state in standby mode or when the oscillator halts. 15.8.1 Features The POE circuit has the following features: * * * Falling edge, P/8 x 16 times, P/16 x 16 times, or P/128 x 16 times low-level sampling can be set for each of input pins POE4 to POE6. The MMT's output pins can be placed in the high-impedance state at the falling edge or lowlevel sampling of pins POE4 to POE6. An interrupt can be generated by input level sampling. High impedance request control signal Interrupt request (MMTPOE) ICSR2 Input level detection circuit POE6 POE5 POE4 Falling edge detection circuit Low level detection circuit P/8 P/16 P/128 Figure 15.18 Block Diagram of POE Rev. 4.00 Dec 05, 2005 page 426 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) 15.8.2 Input/Output Pins Table15.5 shows the pin configuration of the POE circuit. Table 15.5 Pin Configuration Name Port output enable input pins Abbreviation POE4 to POE6 I/O Input Function Input request signals for placing MMT's output pins in high-impedance state 15.8.3 Register Description The POE circuit has the following register. * Input level control/status register (ICSR2) Input Level Control/Status Register (ICSR2): The input level control/status register (ICSR2) is a 16-bit readable/writable register that selects the input mode for pins POE4 to POE6, controls enabling or disabling of interrupts, and holds status information. Bit 15 Initial Bit Name Value 0 R/W R Description Reserved This bit is always read as 0 and should only be written with 0. 14 POE6F 0 R/(W)* POE6 Flag Indicates that a high impedance request has been input to the POE6 pin. [Clearing condition] * * When 0 is written to POE6F after reading POE6F = 1 When the input set by bits 4 and 5 of ICSR2 occurs at the POE6 pin [Setting condition] Rev. 4.00 Dec 05, 2005 page 427 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) Initial Bit Name Value POE5F 0 Bit 13 R/W R/(W)* Description POE5 Flag Indicates that a high impedance request has been input to the POE5 pin. [Clearing condition] * * When 0 is written to POE5F after reading POE5F = 1 When the input set by bits 2 and 3 of ICSR2 occurs at the POE5 pin [Setting condition] 12 POE4F 0 R/(W)* POE4 Flag Indicates that a high impedance request has been input to the POE4 pin. [Clearing condition] * * When 0 is written to POE4F after reading POE4F = 1 When the input set by bits 0 and 1 of ICSR2 occurs at the POE4 pin [Setting condition] 11 to 9 All 0 R Reserved These bits are always read as 0 and should only be written with 0. 8 PIE 0 R/W Port Interrupt Enable Enables or disables an interrupt request when 1 is set in any of bits POE4F to POE6F in ICSR2. 0: Interrupt request disabled 1: Interrupt request enabled 7, 6 All 0 R Reserved These bits are always read as 0 and should only be written with 0. Rev. 4.00 Dec 05, 2005 page 428 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) Initial Bit Name Value POE6M1 POE6M0 0 0 Bit 5 4 R/W R/W R/W Description POE6 Mode 1 and 0 These bits select the input mode of the POE6 pin. 00: Request accepted at falling edge of POE6 input 01: POE6 input is sampled for low level 16 times every P/8 clock, and request is accepted when all samples are low level 10: POE6 input is sampled for low level 16 times every P/16 clock, and request is accepted when all samples are low level 11: POE6 input is sampled for low level 16 times every P/128 clock, and request is accepted when all samples are low level 3 2 POE5M1 POE5M0 0 0 R/W R/W POE5 Mode 1 and 0 These bits select the input mode of the POE5 pin. 00: Request accepted at falling edge of POE5 input 01: POE5 input is sampled for low level 16 times every P/8 clock, and request is accepted when all samples are low level 10: POE5 input is sampled for low level 16 times every P/16 clock, and request is accepted when all samples are low level 11: POE5 input is sampled for low level 16 times every P/128 clock, and request is accepted when all samples are low level 1 0 POE4M1 POE4M0 0 0 R/W R/W POE4 Mode 1 and 0 These bits select the input mode of the POE4 pin. 00: Request accepted at falling edge of POE4 input 01: POE4 input is sampled for low level 16 times every P/8 clock, and request is accepted when all samples are low level 10: POE4 input is sampled for low level 16 times every P/16 clock, and request is accepted when all samples are low level 11: POE4 input is sampled for low level 16 times every P/128 clock, and request is accepted when all samples are low level Note: * Only 0 can be written to clear the flag. Rev. 4.00 Dec 05, 2005 page 429 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) 15.8.4 Operation Input Level Detection: When the input condition set in ICSR2 occurs on any one of the POE pins, the MMT output pins go to the high-impedance state. * Pins placed in the high-impedance state (the MMT's output pins) The six pins PWOB, PWOA, PVOB, PVOA, PUOB, PUOA in the motor management timer (MMT) are placed in the high-impedance state. Note: These pins are in the high-impedance state only when each pin is used as the general input/output function or MMT output pin. 1. Falling edge detection When a transition from high- to low-level input occurs on a POE pin 2. Low level detection Figure 15.19 shows the low level detection operation. Low level sampling is performed 16 times in succession using the sampling clock set in ICSR2. The input is not accepted if a high level is detected even once among these samples. The timing of entry of the MMT's output pins into the high-impedance state from the sampling clock is the same for falling edge detection and low level detection. 8, 16, or 128 clocks P Sampling clock POE input PUOA High-impedance state [1] [1] [2] [2] [3] [16] Flag set (POE accepted) [13] Flag not set All low-level samples At least one high-level sample Note: The other MMT output pins also go to the high-impedance state at the same timing. Figure 15.19 Low Level Detection Operation Rev. 4.00 Dec 05, 2005 page 430 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) Exiting High-Impedance State: The MMT output pins that have entered the high-impedance state by the input level detection are released from this state by restoring them to their initial states by means of a power-on reset, or by clearing all the POE flags in ICSR2 (POE4F to POE6F: bits 12 to 14). 15.8.5 Usage Note 1. To set the POE pin as a level-detective pin, a high level signal must be firstly input to the POE pin. 2. To clear bits POE4F, POE5F, and POE6F to 0, read the ICSR2 register. Clear bits, which are read as 1, to 0, and write 1 to the other bits in the register. Rev. 4.00 Dec 05, 2005 page 431 of 564 REJ09B0270-0400 Section 15 Motor Management Timer (MMT) Rev. 4.00 Dec 05, 2005 page 432 of 564 REJ09B0270-0400 Section 16 Pin Function Controller (PFC) Section 16 Pin Function Controller (PFC) The pin function controller (PFC) is composed of those registers that are used to select the functions of multiplexed pins and assign pins to be inputs or outputs. Tables 16.1 to 16.5 list the multiplexed pins of SH7046 Group devices. Tables 16.6 list the pin functions in each operating mode. Table 16.1 Multiplexed Pins (Port A) Function 1 (Related Module) PA0 I/O (port) PA1 I/O (port) PA2 I/O (port) PA3 I/O (port) PA4 I/O (port) PA5 I/O (port) PA6 I/O (port) PA7 I/O (port) PA8 I/O (port) PA9 I/O (port) PA10 I/O (port) PA11 I/O (port) PA12 I/O (port) PA13 I/O (port) PA14 I/O (port) PA15 I/O (port) Function 2 (Related Module) TCLKA input (MTU) TCLKB input (MTU) TCLKC input (MTU) TCLKD input (MTU) Function 3 (Related Module) IRQ2 input (INTC) IRQ3 input (INTC) Function 4 (Related Module) IRQ0 input (INTC) IRQ1 input (INTC) Function 5 (Related Module) Function 6 (Related Module) POE0 input (port) POE1 input (port) PCIO I/O (MMT) POE4 input (port) POE5 input (port) POE6 input (port) RXD2 input (SCI) TXD2 output (SCI) RXD3 input (SCI) TXD3 output (SCI) SCK2 I/O (SCI) SCK3 I/O (SCI) Function 7 (Related Module) RXD2 input (SCI) TXD2 output (SCI) SCK2 I/O (SCI) RXD3 input (SCI) TXD3 output (SCI) SCK3 I/O (SCI) Function 8 (Related Module) Port A ADTRG input (A/D) UBCTRG output (UBC)* POE4 input (port) POE5 input (port) POE6 input (port) Note: * F-ZTAT only Rev. 4.00 Dec 05, 2005 page 433 of 564 REJ09B0270-0400 Section 16 Pin Function Controller (PFC) Table 16.2 Multiplexed Pins (Port B) Port B Function 1 (Related Module) PB2 I/O (port) PB3 I/O (port) PB4 I/O (port) PB5 I/O (port) Function 2 (Related Module) IRQ0 input (INTC) IRQ1 input (INTC) IRQ2 input (INTC) IRQ3 input (INTC) Function 3 (Related Module) POE0 input (port) POE1 input (port) POE2 input (port) POE3 input (port) Function 4 (Related Module) Table 16.3 Multiplexed Pins (Port E) Port E Function 1 (Related Module) PE0 I/O (port) PE1 I/O (port) PE2 I/O (port) PE3 I/O (port) PE4 I/O (port) PE5 I/O (port) PE6 I/O (port) PE7 I/O (port) PE8 I/O (port) PE9 I/O (port) PE10 I/O (port) PE11 I/O (port) PE12 I/O (port) PE13 I/O (port) PE14 I/O (port) PE15 I/O (port) PE16 I/O (port) PE17 I/O (port) PE18 I/O (port) PE19 I/O (port) PE20 I/O (port) PE21 I/O (port) Note: * F-ZTAT only Function 2 (Related Module) TIOC0A I/O (MTU) TIOC0B I/O (MTU) TIOC0C I/O (MTU) TIOC0D I/O (MTU) TIOC1A I/O (MTU) TIOC1B I/O (MTU) TIOC2A I/O (MTU) TIOC2B I/O (MTU) TIOC3A I/O (MTU) TIOC3B I/O (MTU) TIOC3C I/O (MTU) TIOC3D I/O (MTU) TIOC4A I/O (MTU) TIOC4B I/O (MTU) TIOC4C I/O (MTU) TIOC4D I/O (MTU) Function 3 (Related Module) RXD3 input (SCI) TXD3 output (SCI) SCK3 I/O (SCI) RXD2 input (SCI) SCK2 I/O (SCI) TXD2 output (SCI) MRES input (INTC) Function 4 (Related Module) IRQOUT output (INTC) PUOA output (MMT) UBCTRG output (UBC)* PVOA output (MMT) PWOA output (MMT) PUOB output (MMT) PVOB output (MMT) PWOB output (MMT) Rev. 4.00 Dec 05, 2005 page 434 of 564 REJ09B0270-0400 Section 16 Pin Function Controller (PFC) Table 16.4 Multiplexed Pins (Port F) Port F Function 1 (Related Module) PF8 input (port) PF9 input (port) PF10 input (port) PF11 input (port) PF12 input (port) PF13 input (port) PF14 input (port) PF15 input (port) Function 2 (Related Module) AN8 input (A/D-0) AN9 input (A/D-0) AN10 input (A/D-0) AN11 input (A/D-0) AN12 input (A/D-1) AN13 input (A/D-1) AN14 input (A/D-1) AN15 input (A/D-1) Function 3 (Related Module) Function 4 (Related Module) Table 16.5 Multiplexed Pins (Port G) Port G Function 1 (Related Module) PG0 input (port) PG1 input (port) PG2 input (port) PG3 input (port) Function 2 (Related Module) AN16 input (A/D-2) AN17 input (A/D-2) AN18 input (A/D-2) AN19 input (A/D-2) Function 3 (Related Module) Function 4 (Related Module) Rev. 4.00 Dec 05, 2005 page 435 of 564 REJ09B0270-0400 Section 16 Pin Function Controller (PFC) Table 16.6 Pin Functions in Each Mode Pin Name Single Chip Mode Pin No. 11, 43, 66 9, 24, 41, 64 22, 62 27, 38 25, 40 1 2 3 4 5 6 7 8 10 12 13 14 15 16 17 18 19 20 21 23 26 28 29 30 31 32 Initial Function Vcc Vss VCL AVcc AVss PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PF15/AN15 PF14/AN14 PF13/AN13 PF12/AN12 PG3/AN19 PG2/AN18 PFC Selected Function Possibilities Vcc Vss VCL AVcc AVss PE2/TIOC0C PE3/TIOC0D PE4/TIOC1A/RXD3 PE5/TIOC1B/TXD3 PE6/TIOC2A/SCK3 PE7/TIOC2B/RXD2 PE8/TIOC3A/SCK2 PE9/TIOC3B PE10/TIOC3C/TXD2 PE11/TIOC3D PE12/TIOC4A PE13/TIOC4B/MRES PE14/TIOC4C PE15/TIOC4D/IRQOUT PE16/PUOA/UBCTRG* PE17/PVOA PE18/PWOA PE19/PUOB PE20/PVOB PE21/PWOB PF15/AN15 PF14/AN14 PF13/AN13 PF12/AN12 PG3/AN19 PG2/AN18 Rev. 4.00 Dec 05, 2005 page 436 of 564 REJ09B0270-0400 Section 16 Pin Function Controller (PFC) Pin Name Single Chip Mode Pin No. 33 34 35 36 37 39 42 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 63 65 67 68 69 70 71 Initial Function PG1/AN17 PG0/AN16 PF11/AN11 PF10/AN10 PF9/AN9 PF8/AN8 PB5 PB4 PB3 PB2 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 FWP RES NMI MD3 MD2 MD1 PFC Selected Function Possibilities PG1/AN17 PG0/AN16 PF11/AN11 PF10/AN10 PF9/AN9 PF8/AN8 PB5/IRQ3/POE3 PB4/IRQ2/POE2 PB3/IRQ1/POE1 PB2/IRQ0/POE0 PA15/POE6 PA14/POE5 PA13/POE4 PA12/UBCTRG* PA11/ADTRG/SCK3 PA10/SCK2 PA9/TCLKD/IRQ3/TXD3 PA8/TCLKC/IRQ2/RXD3 PA7/TCLKB/TXD2 PA6/TCLKA/RXD2 PA5/IRQ1/POE6/SCK3 PA4/POE5/TXD3 PA3/POE4/RXD3 PA2/IRQ0/PCIO/SCK2 PA1/POE1/TXD2 PA0/POE0/RXD2 FWP RES NMI MD3 MD2 MD1 Rev. 4.00 Dec 05, 2005 page 437 of 564 REJ09B0270-0400 Section 16 Pin Function Controller (PFC) Pin Name Single Chip Mode Pin No. 72 73 74 75 76 77 78 79 80 Note: * Initial Function MD0 EXTAL XTAL PLLVCL PLLCAP PLLVss WDTOVF PE0 PE1 PFC Selected Function Possibilities MD0 EXTAL XTAL PLLVCL PLLCAP PLLVss WDTOVF PE0/TIOC0A PE1/TIOC0B F-ZTAT only. In single chip mode, do not set functions other than those that can be set by PFC listed in this table. 16.1 Register Descriptions The registers listed below make up the pin function controller (PFC). For details on the addresses of the registers and their states during each process, see appendix A, Internal I/O Register. * Port A I/O register L (PAIORL) * Port A control register L3 (PACRL3) * Port A control register L2 (PACRL2) * Port A control register L1 (PACRL1) * Port B I/O register (PBIOR) * Port B control register 1 (PBCR1) * Port B control register 2 (PBCR2) * Port E I/O register H (PEIORH) * Port E I/O register L (PEIORL) * Port E control register H (PECRH) * Port E control register L1 (PECRL1) * Port E control register L2 (PECRL2) Rev. 4.00 Dec 05, 2005 page 438 of 564 REJ09B0270-0400 Section 16 Pin Function Controller (PFC) 16.1.1 Port A I/O Register L (PAIORL) The port A I/O register L (PAIORL) is a 16-bit readable/writable register that is used to set the pins on port A as inputs or outputs. Bits PA15IOR to PA0IOR correspond to pins PA15 to PA0 (names of multiplexed pins are here given as port names and pin numbers alone). PAIORL is enabled when the port A pins are functioning as general-purpose inputs/outputs (PA15 to PA0), SCK2 and SCK3 pins are functioning as inputs/outputs of SCI, and PCIO pins are functioning as an input/output of MMT. In other states, PAIORL is disabled. A given pin on port A will be an output pin if the corresponding bit in PAIORL is set to 1, and an input pin if the bit is cleared to 0. The initial value of PAIORL is H'0000. 16.1.2 Port A Control Registers L3 to L1 (PACRL3 to PACRL1) The port A control registers L3 to L1 (PACRL3 to PACRL1) are 16-bit readable/writable registers that are used to select the functions of the multiplexed pins on port A. Port A Control Registers L3 to L1 (PACRL3 to PACRL1) Register Bit PACRL3 PACRL1 PACRL1 15 15 14 Bit Name PA15MD2 PA15MD1 PA15MD0 Initial Value 0 0 0 R/W R/W R/W R/W Description PA15 Mode Select the function of the PA15/POE6 pin. 000: PA15 I/O (port) 001: Setting prohibited 010: POE6 input (port) PACRL3 PACRL1 PACRL1 14 13 12 PA14MD2 PA14MD1 PA14MD0 0 0 0 R/W R/W R/W PA14 Mode Select the function of the PA14/POE5 pin. 000: PA14 I/O (port) 001: Setting prohibited 010: POE5 input (port) PACRL3 PACRL1 PACRL1 13 11 10 PA13MD2 PA13MD1 PA13MD0 0 0 0 R/W R/W R/W PA13 Mode Select the function of the PA13/POE4 pin. 000: PA13 I/O (port) 001: Setting prohibited 010: POE4 input (port) 011: Setting prohibited 1xx: Setting prohibited 011: Setting prohibited 1xx: Setting prohibited 011: Setting prohibited 1xx: Setting prohibited Rev. 4.00 Dec 05, 2005 page 439 of 564 REJ09B0270-0400 Section 16 Pin Function Controller (PFC) Initial Value 0 0 0 Register Bit PACRL3 PACRL1 PACRL1 12 9 8 Bit Name PA12MD2 PA12MD1 PA12MD0 R/W R/W R/W R/W Description PA12 Mode Select the function of the PA12/UBCTRG pin. 000: PA12 I/O (port) 001: Setting prohibited 011: Setting prohibited 1xx: Setting prohibited 010: UBCTRG output (UBC)* PACRL3 PACRL1 PACRL1 11 7 6 PA11MD2 PA11MD1 PA11MD0 0 0 0 R/W R/W R/W PA11 Mode Select the function of the PA11/ADTRG/SCK3 pin. 000: PA11 I/O (port) 001: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: SCK3 I/O (SCI) 111: Setting prohibited 010: ADTRG input (A/D) 110: Setting prohibited PACRL3 PACRL1 PACRL1 10 5 4 PA10MD2 PA10MD1 PA10MD0 0 0 0 R/W R/W R/W PA10 Mode Select the function of the PA10/SCK2 pin. 000: PA10 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited PACRL3 PACRL1 PACRL1 9 3 2 PA9MD2 PA9MD1 PA9MD0 0 0 0 R/W R/W R/W PA9 Mode Select the function of the PA9/TCLKD/IRQ3/TXD3 pin. 000: PA9 I/O (port) 010: IRQ3 input (INTC) 011: Setting prohibited PACRL3 PACRL1 PACRL1 8 1 0 PA8MD2 PA8MD1 PA8MD0 0 0 0 R/W R/W R/W PA8 Mode Select the function of the PA8/TCLKC/IRQ2/RXD3 pin. 000: PA8 I/O (port) 010: IRQ2 input (INTC) 011: Setting prohibited 100: Setting prohibited 110: Setting prohibited 111: Setting prohibited 001: TCLKC input (MTU) 101: RXD3 input (SCI) 100: Setting prohibited 110: Setting prohibited 111: Setting prohibited 001: TCLKD input (MTU) 101: TXD3 output (SCI) 100: Setting prohibited 101: SCK2 I/O (SCI) 110: Setting prohibited 111: Setting prohibited Rev. 4.00 Dec 05, 2005 page 440 of 564 REJ09B0270-0400 Section 16 Pin Function Controller (PFC) Initial Value 0 0 0 Register Bit PACRL3 PACRL2 PACRL2 7 15 14 Bit Name PA7MD2 PA7MD1 PA7MD0 R/W R/W R/W R/W Description PA7 Mode Select the function of the PA7/TCLKB/TXD2 pin. 000: PA7 I/O (port) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 110: Setting prohibited 111: Setting prohibited 001: TCLKB input (MTU) 101: TXD2 output (SCI) PACRL3 PACRL2 PACRL2 6 13 12 PA6MD2 PA6MD1 PA6MD0 0 0 0 R/W R/W R/W PA6 Mode Select the function of the PA6/TCLKA/RXD2 pin. 000: PA6 I/O (port) 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 110: Setting prohibited 111: Setting prohibited 001: TCLKA input (MTU) 101: RXD2 input (SCI) PACRL3 PACRL2 PACRL2 5 11 10 PA5MD2 PA5MD1 PA5MD0 0 0 0 R/W R/W R/W PA5 Mode Select the function of the PA5/IRQ1/POE6/SCK3 pin. 000: PA5 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: IRQ1 input (INTC) 100: Setting prohibited 101: POE6 input (port) 110: SCK3 I/O (SCI) 111: Setting prohibited PACRL3 PACRL2 PACRL2 4 9 8 PA4MD2 PA4MD1 PA4MD0 0 0 0 R/W R/W R/W PA4 Mode Select the function of the PA4/POE5/TXD3 pin. 000: PA4 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: POE5 input (port) 110: TXD3 output (SCI) 111: Setting prohibited PACRL3 PACRL2 PACRL2 3 7 6 PA3MD2 PA3MD1 PA3MD0 0 0 0 R/W R/W R/W PA3 Mode Select the function of the PA3/POE4/RXD3 pin. 000: PA3 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: POE4 input (port) 110: RXD3 input (SCI) 111: Setting prohibited Rev. 4.00 Dec 05, 2005 page 441 of 564 REJ09B0270-0400 Section 16 Pin Function Controller (PFC) Initial Value 0 0 0 Register Bit PACRL3 PACRL2 PACRL2 2 5 4 Bit Name PA2MD2 PA2MD1 PA2MD0 R/W R/W R/W R/W Description PA2 Mode Select the function of the PA2/IRQ0/PCIO/SCK2 pin. 000: PA2 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: IRQ0 input (INTC) 100: Setting prohibited 101: PCIO I/O (MMT) 110: SCK2 I/O (SCI) 111: Setting prohibited PACRL3 PACRL2 PACRL2 1 3 2 PA1MD2 PA1MD1 PA1MD0 0 0 0 R/W R/W R/W PA1 Mode Select the function of the PA1/POE1/TXD2 pin. 000: PA1 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: POE1 input (port) 110: TXD2 output (SCI) 111: Setting prohibited PACRL3 PACRL2 PACRL2 0 1 0 PA0MD2 PA0MD1 PA0MD0 0 0 0 R/W R/W R/W PA0 Mode Select the function of the PA0/POE0/RXD2 pin. 000: PA0 I/O (port) 001: Setting prohibited 010: Setting prohibited 011: Setting prohibited 100: Setting prohibited 101: POE0 input (port) 110: RXD2 input (SCI) 111: Setting prohibited Notes: x: Don't care * F-ZTAT only. Setting prohibited for the mask version. 16.1.3 Port B I/O Register (PBIOR) The port B I/O register (PBIOR) is a 16-bit readable/writable register that is used to set the pins on port B as inputs or outputs. Bits PB5IOR to PB2IOR correspond to pins PB5 to PB2 (names of multiplexed pins are here given as port names and pin numbers alone). PBIOR is enabled when port B pins are functioning as general-purpose inputs/outputs (PB5 to PB2). In other states, PBIOR is disabled. A given pin on port B will be an output pin if the corresponding bit in PBIOR is set to 1, and an input pin if the bit is cleared to 0. Bits 15 to 6, bit 1, and bit 0 are reserved. These bits are always read as 0 and should only be written with 0. The initial vale of PBIOR is H'0000. Rev. 4.00 Dec 05, 2005 page 442 of 564 REJ09B0270-0400 Section 16 Pin Function Controller (PFC) 16.1.4 Port B Control Registers 1 and 2 (PBCR1 and PBCR2) The port B control registers 1 and 2 (PBCR1 and PBCR2) are 16-bit readable/writable registers that are used to select the multiplexed pin function of the pins on port B. Note that the bit 9 of PBCR1 and bits 3 to 0 of PBCR2 are disabled. Port B Control Registers 1 and 2 (PBCR1 and PBCR2) Register Bit PBCR1 PBCR1 PBCR1 PBCR2 PBCR2 PBCR1 PBCR2 PBCR2 15, 14 8 to 0 9 3 to 0 13 11 10 Bit Name PB5MD2 PB5MD1 PB5MD0 Initial Value All 0 All 0 0 All 0 All 0 0 0 0 R/W R R R R R R/W R/W R/W PB5 Mode Select the function of the PB5/IRQ3/POE3 pin. 000: PB5 I/O (port) 010: POE3 input (port) PBCR1 PBCR2 PBCR2 12 9 8 PB4MD2 PB4MD1 PB4MD0 0 0 0 R/W R/W R/W PB4 Mode Select the function of the PB4/IRQ2/POE2 pin. 000: PB4 I/O (port) 010: POE2 input (port) PBCR1 PBCR2 PBCR2 11 7 6 PB3MD2 PB3MD1 PB3MD0 0 0 0 R/W R/W R/W PB3 Mode Select the function of the PB3/IRQ1/POE1 pin. 000: PB3 I/O (port) 010: POE1 input (port) PBCR1 PBCR2 PBCR2 10 5 4 PB2MD2 PB2MD1 PB2MD0 0 0 0 R/W R/W R/W PB2 Mode Select the function of the PB2/IRQ0/POE0 pin. 000: PB2 I/O (port) 010: POE0 input (port) Note: x: Don't care 011: Setting prohibited 001: IRQ0 input (INTC) 1xx: Setting prohibited 011: Setting prohibited 001: IRQ1 input (INTC) 1xx: Setting prohibited 011: Setting prohibited 001: IRQ2 input (INTC) 1xx: Setting prohibited 011: Setting prohibited 001: IRQ3 input (INTC) 1xx: Setting prohibited Description Reserved These bits are always read as 0 and should only be written with 0. 15 to 12 Rev. 4.00 Dec 05, 2005 page 443 of 564 REJ09B0270-0400 Section 16 Pin Function Controller (PFC) 16.1.5 Port E I/O Registers L and H (PEIORL and PEIORH) The port E I/O registers L and H (PEIORL and PEIORH) are 16-bit readable/writable registers that are used to set the pins on port E as inputs or outputs. Bits PE21IOR to PE0IOR correspond to pins PE21 to PE0 (names of multiplexed pins are here given as port names and pin numbers alone). PEIORL is enabled when the port E pins are functioning as general-purpose inputs/outputs (PE15 to PD0), TIOC pins are functioning as inputs/outputs of MTU, and SCK2 and SCK3 pins are functioning as inputs/outputs of SCI. In other states, PEIORL is disabled. PEIORH is enabled when the port E pins are functioning as general-purpose inputs/outputs (PE21 to PE16). In other states, PEIORH is disabled. A given pin on port E will be an output pin if the corresponding PEIORL or PEIORH bit is set to 1, and an input pin if the bit is cleared to 0. Bits 15 to 6 of PEIORH are reserved. These bits are always read as 0 and should only be written with 0. The initial values of PEIORL and PEIORH are H'0000. Rev. 4.00 Dec 05, 2005 page 444 of 564 REJ09B0270-0400 Section 16 Pin Function Controller (PFC) 16.1.6 Port E Control Registers L1, L2, and H (PECRL1, PECRL2, and PECRH) The port E control registers L1, L2, and H (PECRL1, PECRL2 and PECRH) are 16-bit readable/writable registers that are used to select the multiplexed pin function of the pins on port E. Port E Control Registers L1, L2, and H (PECRL1, PECRL2, and PECRH) Register Bit PECRH 15 to 12 11 10 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0 and should only be written with 0. PE21MD1 PE21MD0 0 0 R/W R/W PE21 Mode Select the function of the PE21/PWOB pin. 00: PE21 I/O (port) PECRH PECRH 9 8 PE20MD1 PE20MD0 0 0 R/W R/W PE20 Mode Select the function of the PE20/PVOB pin. 00: PE20 I/O (port) PECRH PECRH 7 6 PE19MD1 PE19MD0 0 0 R/W R/W PE19 Mode Select the function of the PE19/PUOB pin. 00: PE19 I/O (port) PECRH PECRH 5 4 PE18MD1 PE18MD0 0 0 R/W R/W PE18 Mode Select the function of the PE18/PWOA pin. 00: PE18 I/O (port) PECRH PECRH 3 2 PE17MD1 PE17MD0 0 0 R/W R/W PE17 Mode Select the function of the PE17/PVOA pin. 00: PE17 I/O (port) PECRH PECRH 1 0 PE16MD1 PE16MD0 0 0 R/W R/W PE16 Mode Select the function of the PE16/PUOA/UBCTRG pin. 00: PE16 I/O (port) 10: UBCTRG output (UBC)* 01: PUOA output (MMT) 11: Setting prohibited 10: Setting prohibited 01: PVOA output (MMT) 11: Setting prohibited 10: Setting prohibited 01: PWOA output (MMT) 11: Setting prohibited 10: Setting prohibited 01: PUOB output (MMT) 11: Setting prohibited 10: Setting prohibited 01: PVOB output (MMT) 11: Setting prohibited 10: Setting prohibited 01: PWOB output (MMT) 11: Setting prohibited PECRH PECRH Rev. 4.00 Dec 05, 2005 page 445 of 564 REJ09B0270-0400 Section 16 Pin Function Controller (PFC) Initial Value 0 0 Register Bit PECRL1 PECRL1 15 14 Bit Name PE15MD1 PE15MD0 R/W R/W R/W Description PE15 Mode Select the function of the PE15/TIOC4D/IRQOUT pin. 00: PE15 I/O (port) 10: Setting prohibited 01: TIOC4D I/O (MTU) 11: IRQOUT output (INTC) PECRL1 PECRL1 13 12 PE14MD1 PE14MD0 0 0 R/W R/W PE14 Mode Select the function of the PE14/TIOC4C pin. 00: PE14 I/O (port) 10: Setting prohibited 01: TIOC4C I/O (MTU) 11: Setting prohibited PECRL1 PECRL1 11 10 PE13MD1 PE13MD0 0 0 R/W R/W PE13 Mode Select the function of the PE13/TIOC4B/MRES pin. 00: PE13 I/O (port) 10: MRES input (INTC) 01: TIOC4B I/O (MTU) 11: Setting prohibited PECRL1 PECRL1 9 8 PE12MD1 PE12MD0 0 0 R/W R/W PE12 Mode Select the function of the PE12/TIOC4A pin. 00: PE12 I/O (port) 10: Setting prohibited 01: TIOC4A I/O (MTU) 11: Setting prohibited PECRL1 PECRL1 7 6 PE11MD1 PE11MD0 0 0 R/W R/W PE11 Mode Select the function of the PE11/TIOC3D pin. 00: PE11 I/O (port) 10: Setting prohibited 01: TIOC3D I/O (MTU) 11: Setting prohibited PECRL1 PECRL1 5 4 PE10MD1 PE10MD0 0 0 R/W R/W PE10 Mode Select the function of the PE10/TIOC3C/TXD2 pin. 00: PE10 I/O (port) 10: TXD2 output (SCI) 01: TIOC3C I/O (MTU) 11: Setting prohibited PECRL1 PECRL1 3 2 PE9MD1 PE9MD0 0 0 R/W R/W PE9 Mode Select the function of the PE9/TIOC3B pin. 00: PE9 I/O (port) 10: Setting prohibited 01: TIOC3B I/O (MTU) 11: Setting prohibited PECRL1 PECRL1 1 0 PE8MD1 PE8MD0 0 0 R/W R/W PE8 Mode Select the function of the PE8/TIOC3A/SCK2 pin. 00: PE8 I/O (port) 10: SCK2 I/O (SCI) 01: TIOC3A I/O (MTU) 11: Setting prohibited Rev. 4.00 Dec 05, 2005 page 446 of 564 REJ09B0270-0400 Section 16 Pin Function Controller (PFC) Initial Value 0 0 Register Bit PECRL2 PECRL2 15 14 Bit Name PE7MD1 PE7MD0 R/W R/W R/W Description PE7 Mode Select the function of the PE7/TIOC2B/RXD2 pin. 00: PE7 I/O (port) 10: RXD2 input (SCI) 01: TIOC2B I/O (MTU) 11: Setting prohibited PECRL2 PECRL2 13 12 PE6MD1 PE6MD0 0 0 R/W R/W PE6 Mode Select the function of the PE6/TIOC2A/SCK3 pin. 00: PE6 I/O (port) 10: SCK3 I/O (SCI) 01: TIOC2A I/O (MTU) 11: Setting prohibited PECRL2 PECRL2 11 10 PE5MD1 PE5MD0 0 0 R/W R/W PE5 Mode Select the function of the PE5/TIOC1B/TXD3 pin. 00: PE5 I/O (port) 10: TXD3 output (SCI) 01: TIOC1B I/O (MTU) 11: Setting prohibited PECRL2 PECRL2 9 8 PE4MD1 PE4MD0 0 0 R/W R/W PE4 Mode Select the function of the PE4/TIOC1A/RXD3 pin. 00: PE4 I/O (port) 10: RXD3 input (SCI) 01: TIOC1A I/O (MTU) 11: Setting prohibited PECRL2 PECRL2 7 6 PE3MD1 PE3MD0 0 0 R/W R/W PE3 Mode Select the function of the PE3/TIOC0D pin. 00: PE3 I/O (port) 10: Setting prohibited 01: TIOC0D I/O (MTU) 11: Setting prohibited PECRL2 PECRL2 5 4 PE2MD1 PE2MD0 0 0 R/W R/W PE2 Mode Select the function of the PE2/TIOC0C pin. 00: PE2 I/O (port) 10: Setting prohibited 01: TIOC0C I/O (MTU) 11: Setting prohibited PECRL2 PECRL2 3 2 PE1MD1 PE1MD0 0 0 R/W R/W PE1 Mode Select the function of the PE1/TIOC0B pin. 00: PE1 I/O (port) 10: Setting prohibited 01: TIOC0B I/O (MTU) 11: Setting prohibited PECRL2 PECRL2 1 0 PE0MD1 PE0MD0 0 0 R/W R/W PE0 Mode Select the function of the PE0/TIOC0A pin. 00: PE0 I/O (port) 10: Setting prohibited 01: TIOC0A I/O (MTU) 11: Setting prohibited Note: * F-ZTAT only. Setting prohibited for the mask version Rev. 4.00 Dec 05, 2005 page 447 of 564 REJ09B0270-0400 Section 16 Pin Function Controller (PFC) 16.2 Usage Notes (1) In this LSI Group, individual functions are available as multiplexed functions on multiple pins. This approach is intended to increase the number of selectable pin functions and to allow the easier design of boards. When the pin function controller (PFC) is used to select a function, only a single pin can be specified for each function. If one function is specified for two or more pins, the function will not work properly. (2) To select a pin function, set the port control registers (PACRL3, PACRL2, PACRL1, PBCR1 and PBCR2) before setting the port I/O registers (PAIORL and PBIOR). To select the function of the pin which is multiplexed with the port E, the order of setting the port control registers (PECRH, PECRL1, and PECRL2) and port I/O registers (PEIORH and PEIORL) is not matter. (3) Regarding the pin in which input/output port is multiplexed with IRQ, when the port input is changed from low level to IRQ edge detection mode, the corresponding edge is detected. (4) In a state where the pin is in general I/O mode and set to 1-output (specifically, the port control register is in general I/O mode and both the port I/O register and the port data register are set to 1), a power-on reset through the RES pin may generate a low level on this pin upon the poweron state is realized. To prevent this low level from happening, set the port I/O register to 0 (general output) and then apply the power-on reset. Note, however, that no low level may be generated internally by the power-on reset due to the WDT overflow. Rev. 4.00 Dec 05, 2005 page 448 of 564 REJ09B0270-0400 Section 17 I/O Ports Section 17 I/O Ports This LSI has five ports: A, B, E, F, and G. Port A is a 16-bit port, port B is a 4-bit port, and port E is a 22-bit port, all supporting both input and output. Port F is an 8-bit port and port G is a 4-bit port, both for input-only. All the port pins are multiplexed as general input/output pins and special function pins. The functions of the multiplex pins are selected by means of the pin function controller (PFC). Each port is provided with a data register for storing the pin data. 17.1 Port A Port A is an input/output port with the 16 pins shown in figure 17.1. PA15 (I/O) / POE6 (input) PA14 (I/O) / POE5 (input) PA13 (I/O) / POE4 (input) PA12 (I/O) / UBCTRG (output)* PA11 (I/O) / ADTRG (input) / SCK3 (I/O) PA10 (I/O) / SCK2 (I/O) PA9 (I/O) / TCLKD (input) / IRQ3 (input) / TXD3 (output) Port A PA8 (I/O) / TCLKC (input) / IRQ2 (input) / RXD3 (input) PA7 (I/O) / TCLKB (input) / TXD2 (output) PA6 (I/O) / TCLKA (input) / RXD2 (input) PA5 (I/O) / IRQ1 (input) / POE6 (input) / SCK3 (I/O) PA4 (I/O) / POE5 (input) / TXD3 (output) PA3 (I/O) / POE4 (input) / RXD3 (input) PA2 (I/O) / IRQ0 (input) / PCIO (I/O) / SCK2 (I/O) PA1 (I/O) / POE1 (input) / TXD2 (output) PA0 (I/O) / POE0 (input) / RXD2 (input) Note: * Only for the F-ZTAT version (no corresponding function in the mask version.) Figure 17.1 Port A Rev. 4.00 Dec 05, 2005 page 449 of 564 REJ09B0270-0400 Section 17 I/O Ports 17.1.1 Register Description Port A is a 16-bit input/output port. Port A has the following register. For details on register addresses and register states during each processing, refer to appendix A, Internal I/O Register. * Port A data register L (PADRL) 17.1.2 Port A Data Register L (PADRL) The port A data register L (PADRL) is a 16-bit readable/writable register that stores port A data. Bits PA15DR to PA0DR correspond to pins PA15 to PA0 (multiplexed functions omitted here). When a pin functions is a general output, if a value is written to PADRL, that value is output directly from the pin, and if PADRL is read, the register value is returned directly regardless of the pin state. When a pin functions is a general input, if PADRL is read, the pin state, not the register value, is returned directly. If a value is written to PADRL, although that value is written into PADRL, it does not affect the pin state. Table 17.1 summarizes port A data register L read/write operations. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PA15DR PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description See table 17.1 Rev. 4.00 Dec 05, 2005 page 450 of 564 REJ09B0270-0400 Section 17 I/O Ports Table 17.1 Port A Data Register L (PADRL) Read/Write Operations Bits 15 to 0: PAIORL 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PADRL value PADRL value Write Can write to PADRL, but it has no effect on pin state Can write to PADRL, but it has no effect on pin state Value written is output from pin Can write to PADRL, but it has no effect on pin state 17.2 Port B Port B is an input/output port with the four pins shown in figure 17.2. PB5 (I/O) / IRQ3 (input) / POE3 (input) Port B PB4 (I/O) / IRQ2 (input) / POE2 (input) PB3 (I/O) / IRQ1 (input) / POE1 (input) PB2 (I/O) / IRQ0 (input) / POE0 (input) Figure 17.2 Port B 17.2.1 Register Descriptions Port B is a 4-bit input/output port. Port B has the following register. For details on register addresses and register states during each processing, refer to appendix A, Internal I/O Register. * Port B data register (PBDR) Rev. 4.00 Dec 05, 2005 page 451 of 564 REJ09B0270-0400 Section 17 I/O Ports 17.2.2 Port B Data Register (PBDR) The port B data register (PBDR) is a 16-bit readable/writable register that stores port B data. Bits PB5DR to PB2DR correspond to pins PB5 to PB2 (multiplexed functions omitted here). When a pin functions is a general output, if a value is written to PBDR, that value is output directly from the pin, and if PBDR is read, the register value is returned directly regardless of the pin state. When a pin functions is a general input, if PBDR is read, the pin state, not the register value, is returned directly. If a value is written to PBDR, although that value is written into PBDR, it does not affect the pin state. Table 17.2 summarizes port B data register read/write operations. Bit 15 to 6 5 4 3 2 1, 0 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0, and should only be written with 0. PB5DR PB4DR PB3DR PB2DR 0 0 0 0 All 0 R/W R/W R/W R/W R Reserved These bits are always read as 0, and should only be written with 0. See table 17.2 Table 17.2 Port B Data Register (PBDR) Read/Write Operations Bits 5 to 2: PBIOR 0 Pin Function General input Other than general input 1 General output Other than general output Read Pin state Pin state PBDR value PBDR value Write Can write to PBDR, but it has no effect on pin state Can write to PBDR, but it has no effect on pin state Value written is output from pin Can write to PBDR, but it has no effect on pin state Rev. 4.00 Dec 05, 2005 page 452 of 564 REJ09B0270-0400 Section 17 I/O Ports 17.3 Port E Port E is an input/output port with the 22 pins shown in figure 17.3. PE21 (I/O) / PWOB (output) PE20 (I/O) / PVOB (output) PE19 (I/O) / PUOB (output) PE18 (I/O) / PWOA (output) PE17 (I/O) / PVOA (output) PE16 (I/O) / PUOA (output) / UBCTRG (output)* PE15 (I/O) / TIOC4D (I/O) / IRQOUT (output) PE14 (I/O) / TIOC4C (I/O) PE13 (I/O) / TIOC4B (I/O) / MRES (input) Port E PE12 (I/O) / TIOC4A (I/O) PE11 (I/O) / TIOC3D (I/O) PE10 (I/O) / TIOC3C (I/O) / TXD2 (output) PE9 (I/O) / TIOC3B (I/O) PE8 (I/O) / TIOC3A (I/O) / SCK2 (I/O) PE7 (I/O) / TIOC2B (I/O) / RXD2 (input) PE6 (I/O) / TIOC2A (I/O) / SCK3 (I/O) PE5 (I/O) / TIOC1B (I/O) / TXD3 (output) PE4 (I/O) / TIOC1A (I/O) / RXD3 (input) PE3 (I/O) / TIOC0D (I/O) PE2 (I/O) / TIOC0C (I/O) PE1 (I/O) / TIOC0B (I/O) PE0 (I/O) / TIOC0A (I/O) Note: * Only for the F-ZTAT version (no corresponding function in the mask version.) Figure 17.3 Port E Rev. 4.00 Dec 05, 2005 page 453 of 564 REJ09B0270-0400 Section 17 I/O Ports 17.3.1 Register Descriptions Port E has the following registers. For details on register addresses and register states during each processing, refer to appendix A, Internal I/O Register. * Port E data register H (PEDRH) * Port E data register L (PEDRL) 17.3.2 Port E Data Registers H and L (PEDRH and PEDRL) The port E data registers H and L (PEDRH and PEDRL) are 16-bit readable/writable registers that store port E data. Bits PE21DR to PE0DR correspond to pins PE21 to PE0 (multiplexed functions omitted here). When a pin functions is a general output, if a value is written to PEDRH or PEDRL, that value is output directly from the pin, and if PEDRH or PEDRL is read, the register value is returned directly regardless of the pin state. When a pin functions is a general input, if PEDRH or PEDRL is read, the pin state, not the register value, is returned directly. If a value is written to PEDRH or PEDRL, although that value is written into PEDRH or PEDRL it does not affect the pin state. Table 17.3 summarizes port E data register read/write operations. PEDRH: Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0, and should only be written with 0. 5 4 3 2 1 0 PE21DR PE20DR PE19DR PE18DR PE17DR PE16DR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W See table 17.3. 15 to 6 Rev. 4.00 Dec 05, 2005 page 454 of 564 REJ09B0270-0400 Section 17 I/O Ports PEDRL: Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Name PE15DR PE14DR PE13DR PE12DR PE11DR PE10DR PE9DR PE8DR PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description See table 17.3. Table 17.3 Port E Data Registers H and L (PEDRH and PEDRL) Read/Write Operations Bits 5 to 0 in PEDRH and bits 15 to 0 in PEDRL: PEIOR 0 Pin Function General input Other than general input 1 General output Read Pin state Pin state PEDRH or PEDRL value PEDRH or PEDRL value Write Can write to PEDRH or PEDRL, but it has no effect on pin state Can write to PEDRH or PEDRL, but it has no effect on pin state Value written is output from pin (POE pin = high)* High impedance regardless of PEDRH or PEDRL value (POE pin = low)* Can write to PEDRH or PEDRL, but it has no effect on pin state Other than general output Note: * Control by the POE pin is only available for high current-output pins (PE9 and PE11 to PE21). Rev. 4.00 Dec 05, 2005 page 455 of 564 REJ09B0270-0400 Section 17 I/O Ports 17.4 Port F Port F is an input-only port with the eight pins shown in figure 17.4. PF15 (input) / AN15 (input) PF14 (input) / AN14 (input) PF13 (input) / AN13 (input) Port F PF12 (input) / AN12 (input) PF11 (input) / AN11 (input) PF10 (input) / AN10 (input) PF9 (input) / AN9 (input) PF8 (input) / AN8 (input) Figure 17.4 Port F 17.4.1 Register Description Port F is an 8-bit input-only port. Port F has the following register. For details on register addresses and register states during each processing, refer to appendix A, Internal I/O Register. * Port F data register (PFDR) 17.4.2 Port F Data Register (PFDR) The port F data register (PFDR) is a 16-bit read-only register that stores port F data. Bits PF15DR to PF8DR correspond to pins PF15 to PF8 (multiplexed functions omitted here). Any value written into these bits is ignored, and there is no effect on the state of the pins. When any of the bits are read, the pin state rather than the bit value is read directly. However, when an A/D converter analog input is being sampled, values of 1 are read out. Table 17.4 summarizes port F data register read/write operations. Rev. 4.00 Dec 05, 2005 page 456 of 564 REJ09B0270-0400 Section 17 I/O Ports Initial Value 0/1* 0/1* 0/1* 0/1* 0/1* 0/1* 0/1* 0/1* Bit 15 14 13 12 11 10 9 8 7 to 0 Bit Name PF15DR PF14DR PF13DR PF12DR PF11DR PF10DR PF9DR PF8DR R/W R R R R R R R R R Description See table 17.4. Reserved There is no pin corresponding to the bit. These bits are always read as an invalid value. Note: * Initial values are dependent on the state of the external pins. Table 17.4 Port F Data Register (PFDR) Read/Write Operations Bits 15 to 8: Pin I/O Input Pin Function General input ANn input Read Pin state 1 Write Ignored (no effect on pin state) Ignored (no effect on pin state) 17.5 Port G Port G is an input-only port with the 4 pins shown in figure 17.5. PG3 (input) / AN19 (input) PG2 (input) / AN18 (input) Port G PG1 (input) / AN17 (input) PG0 (input) / AN16 (input) Figure 17.5 Port G Rev. 4.00 Dec 05, 2005 page 457 of 564 REJ09B0270-0400 Section 17 I/O Ports 17.5.1 Register Description Port G is a 4-bit input-only port. Port G has the following register. For details on register addresses and register states during each processing, refer to appendix A, Internal I/O Register. * Port G data register (PGDR) 17.5.2 Port G Data Register (PGDR) The port G data register (PGDR) is an 8-bit read-only register that stores port G data. Bits PG3DR to PG0DR correspond to pins PG3 to PG0 (multiplexed functions omitted here). Any value written into these bits is ignored, and there is no effect on the state of the pins. When any of the bits are read, the pin state rather than the bit value is read directly. However, when an A/D converter analog input is being sampled, values of 1 are read out. Table 17.5 summarizes port G data register read/write operations. Bit 7 to 4 3 2 1 0 Note: Bit Name PG3DR PG2DR PG1DR PG0DR * Initial Value All 0 0/1* 0/1* 0/1* 0/1* R/W R R R R R Description Reserved These bits are always read as 0. See table 17.5. Initial values are dependent on the state of the external pins. Table 17.5 Port G Data Register (PGDR) Read/Write Operations Bits 3 to 0: Pin I/O Input Pin Function General input ANn input Read Pin state 1 Write Ignored (no effect on pin state) Ignored (no effect on pin state) Rev. 4.00 Dec 05, 2005 page 458 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) Section 18 Flash Memory (F-ZTAT Version) The features of the flash memory in the flash memory version are summarized below. The block diagram of the flash memory is shown in figure 18.1. 18.1 Features * Size: 256 kbytes * Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows: 64 kbytes x 3 blocks, 32 kbytes x 1 block, and 4 kbytes x 8 blocks. To erase the entire flash memory, each block must be erased in turn. * Reprogramming capability For details, see section 22, Electrical Characteristics. * Two on-board programming modes Boot mode User program mode On-board programming/erasing can be done in boot mode, in which the boot program built into the chip is started to erase or program of the entire flash memory. In normal user program mode, individual blocks can be erased or programmed on board. * PROM Programmer mode Flash memory can be programmed/erased in programmer mode using a PROM programmer, as well as in on-board programming mode. * Automatic bit rate adjustment With data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host. * Programming/erasing protection Sets software protection against flash memory programming/erasing/verifying. ROM3250A_000020020700 Rev. 4.00 Dec 05, 2005 page 459 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) Internal address bus Internal data bus (32 bits) Module bus FLMCR1 FLMCR2 EBR1 EBR2 RAMER Bus interface/controller Operating mode FWP pin Mode pin Flash memory (256 kbytes) Legend: FLMCR1: FLMCR2: EBR1: EBR2: RAMER: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Figure 18.1 Block Diagram of Flash Memory 18.2 Mode Transitions When the mode pin and the FWP pin are set in the reset state and a reset-start is executed, this LSI enters an operating mode as shown in figure 18.2. In user mode, flash memory can be read but not programmed or erased. The boot, user program, and PROM programmer modes are provided as modes to write and erase the flash memory. The differences between boot mode and user program mode are shown in table 18.1. Rev. 4.00 Dec 05, 2005 page 460 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) Figure 18.3 shows boot mode, and figure 18.4 shows user program mode. MD1 = 1, FWP = 1 *1 User mode (on-chip ROM enabled) RES = 0 Reset state MD1 = 1, FWP = 0 RES = 0 RES = 0 *2 RES = 0 PROM Programmer mode FWP = 0 FWP = 1 MD1 = 0, FWP = 0 *1 User program mode Boot mode On-board programming mode Notes: Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory. 1. RAM emulation possible 2. This LSI transits to programmer mode by using the dedicated PROM programmer. Figure 18.2 Flash Memory State Transitions Table 18.1 Differences between Boot Mode and User Program Mode Boot Mode Total erase Block erase Programming control program* Yes No (2) User Program Mode Yes Yes (1) (2) (3) (1) Erase/erase-verify (2) Program/program-verify (3) Emulation Note: * To be provided by the user, in accordance with the recommended algorithm. Rev. 4.00 Dec 05, 2005 page 461 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in this LSI (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication. The boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Host Programming control program New application program New application program This LSI Boot program Flash memory RAM SCI This LSI Boot program Flash memory RAM Boot program area SCI Application program (old version) Application program (old version) Programming control program 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, total flash memory erasure is performed, without regard to blocks. Host 4. Writing new application program The programming control program transferred from the host to RAM is executed, and the new application program in the host is written into the flash memory. Host New application program This LSI Boot program Flash memory RAM Boot program area Flash memory erase Programming control program This LSI SCI Boot program Flash memory RAM Boot program area New application program Programming control program SCI Program execution state Figure 18.3 Boot Mode Rev. 4.00 Dec 05, 2005 page 462 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) 1. Initial state The FWE assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. The programming/erase control program should be prepared in the host or in the flash memory. Host Programming/ erase control program New application program 2. Programming/erase control program transfer When user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to RAM. Host New application program This LSI Boot program Flash memory FWE assessment program This LSI SCI RAM Boot program Flash memory FWE assessment program SCI RAM Transfer program Transfer program Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. Host 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host New application program This LSI Boot program Flash memory FWE assessment program This LSI SCI RAM Boot program Flash memory FWE assessment program Transfer program Programming/ erase control program Programming/ erase control program SCI RAM Transfer program Flash memory erase New application program Program execution state Figure 18.4 User Program Mode Rev. 4.00 Dec 05, 2005 page 463 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) 18.3 Block Configuration Figure 18.5 shows the block configuration of 256-kbyte flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 64 kbytes (3 blocks), 32 kbytes (1 block), and 4 kbytes (8 blocks). Erasing is performed in these units. Programming is performed in 128-byte units starting from an address with lower eight bits H'00 or H'80. EB0 Erase unit 4 kbytes EB1 Erase unit 4 kbytes EB2 Erase unit 4 kbytes EB3 Erase unit 4 kbytes EB4 Erase unit 4 kbytes EB5 Erase unit 4 kbytes EB6 Erase unit 4 kbytes EB7 Erase unit 4 kbytes EB8 Erase unit 32 kbytes EB9 Erase unit 64 kbytes EB10 Erase unit 64 kbytes EB11 Erase unit 64 kbytes H'003000 H'002000 H'001000 H'000000 Programming unit: 128 bytes -------------------- H'00007F H'000FFF Programming unit: 128 bytes -------------------- H'001FFF Programming unit: 128 bytes -------------------- Programming unit: 128 bytes H'002FFF -------------------- H'004000 Programming unit: 128 bytes -------------------- H'005000 Programming unit: 128 bytes -------------------- H'006000 Programming unit: 128 bytes -------------------- H'007000 Programming unit: 128 bytes -------------------- H'008000 Programming unit: 128 bytes -------------------- H'010000 Programming unit: 128 bytes -------------------- H'020000 Programming unit: 128 bytes -------------------- H'030000 Programming unit: 128 bytes -------------------- H'003FFF H'004FFF H'005FFF H'006FFF H'007FFF H'00FFFF H'01FFFF H'02FFFF H'03FFFF Figure 18.5 Flash Memory Block Configuration Rev. 4.00 Dec 05, 2005 page 464 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) 18.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 18.2. Table 18.2 Pin Configuration Pin Name RES FWP MD1 MD0 TxD3 (PA9)* RxD3 (PA8)* Note: * I/O Input Input Input Input Output Input Function Reset Flash program/erase protection by hardware Sets this LSI's operating mode Sets this LSI's operating mode Serial transmit data output Serial receive data input In boot mode, PA8 and PA9 pins are used as SCI pins. 18.5 Register Descriptions The flash memory has the following registers. For details on register addresses and register states during each processing, refer to appendix A, Internal I/O Register. * Flash memory control register 1 (FLMCR1) * Flash memory control register 2 (FLMCR2) * Erase block register 1 (EBR1) * Erase block register 2 (EBR2) * RAM emulation register (RAMER) 18.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 18.8, Flash Memory Programming/Erasing. Rev. 4.00 Dec 05, 2005 page 465 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) Initial Value 1/0 Bit 7 Bit Name FWE R/W R Description Flash Write Enable Reflects the input level at the FWP pin. It is set to 1 when a low level is input to the FWP pin, and cleared to 0 when a high level is input. 6 SWE 0 R/W Software Write Enable When this bit is set to 1 while the FWE bit is 1, flash memory programming/erasing is enabled. When this bit is cleared to 0, other FLMCR1 bits and all EBR1 and EBR2 bits cannot be set. 5 ESU 0 R/W Erase Setup When this bit is set to 1 while the FWE and SWE bits are 1, the flash memory changes to the erase setup state. When it is cleared to 0, the erase setup state is cancelled. 4 PSU 0 R/W Program Setup When this bit is set to 1 while the FWE and SWE bits are 1, the flash memory changes to the program setup state. When it is cleared to 0, the program setup state is cancelled. 3 EV 0 R/W Erase-Verify When this bit is set to 1 while the FWE and SWE bits are 1, the flash memory changes to erase-verify mode. When it is cleared to 0, erase-verify mode is cancelled. 2 PV 0 R/W Program-Verify When this bit is set to 1 while the FWE and SWE bits are 1, the flash memory changes to program-verify mode. When it is cleared to 0, program-verify mode is cancelled. 1 E 0 R/W Erase When this bit is set to 1 while the FWE, SWE and ESU bits are 1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled. 0 P 0 R/W Program When this bit is set to 1 while the FWE, SWE and PSU bits are 1, the flash memory changes to program mode. When it is cleared to 0, program mode is cancelled. Rev. 4.00 Dec 05, 2005 page 466 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) 18.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. Bit 7 Bit Name FLER Initial Value 0 R/W R Description Indicates that an error has occurred during an operation on flash memory (programming or erasing). When flash memory goes to the error-protection state, FLER is set to 1. See section 18.9.3, Error Protection, for details. 6 to 0 All 0 R Reserved These bits are always read as 0. 18.5.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase block. EBR1 is initialized to H'00 when a high level is input to the FWP pin. It is also initialized to H'00, when the SWE bit in FLMCR1 is 0 regardless of value in the FWP pin. Do not set more than one bit at a time in EBR1 and EBR2, as this will cause all the bits in EBR1 and EBR2 to be automatically cleared to 0. Bit 7 6 5 4 3 2 1 0 Bit Name EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description When this bit is set to 1, 4 kbytes of EB7 (H'007000 to H'007FFF) are to be erased. When this bit is set to 1, 4 kbytes of EB6 (H'006000 to H'006FFF) are to be erased. When this bit is set to 1, 4 kbytes of EB5 (H'005000 to H'005FFF) are to be erased. When this bit is set to 1, 4 kbytes of EB4 (H'004000 to H'004FFF) are to be erased. When this bit is set to 1, 4 kbytes of EB3 (H'003000 to H'003FFF) are to be erased. When this bit is set to 1, 4 kbytes of EB2 (H'002000 to H'002FFF) are to be erased. When this bit is set to 1, 4 kbytes of EB1 (H'001000 to H'001FFF) are to be erased. When this bit is set to 1, 4 kbytes of EB0 (H'000000 to H'000FFF) are to be erased. Rev. 4.00 Dec 05, 2005 page 467 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) 18.5.4 Erase Block Register 2 (EBR2) EBR2 specifies the flash memory erase block. EBR2 is initialized to H'00 when a high level is input to the FWP pin. It is also initialized to H'00, when the SWE bit in FLMCR1 is 0 regardless of value in the FWP pin. Do not set more than one bit at a time in EBR1 and EBR2, as this will cause all the bits in EBR1 and EBR2 to be automatically cleared to 0. Bit 7 to 4 Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0 and should only be written with 0 3 2 1 0 EB11 EB10 EB9 EB8 0 0 0 0 R/W R/W R/W R/W When this bit is set to 1, 64 kbytes of EB11 (H'030000 to H'03FFFF) are to be erased. When this bit is set to 1, 64 kbytes of EB10 (H'020000 to H'02FFFF) are to be erased. When this bit is set to 1, 64 kbytes of EB9 (H'010000 to H'01FFFF) will be erased. When this bit is set to 1, 32 kbytes of EB8 (H'008000 to H'00FFFF) will be erased. Rev. 4.00 Dec 05, 2005 page 468 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) 18.5.5 RAM Emulation Register (RAMER) RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating real-time flash memory programming. RAMER settings should be made in user mode or user program mode. To ensure correct operation of the emulation function, the ROM for which RAM emulation is performed should not be accessed immediately after this register has been modified. Normal execution of an access immediately after register modification is not guaranteed. Bit 15 to 4 3 Bit Name RAMS Initial Value All 0 0 R/W R R/W Description Reserved These bits are always read as 0. RAM Select Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, the flash memory is overlapped with part of RAM, and all flash memory blocks are program/erase-protected. When RAMS = 0, the RAM emulation function is disabled. 2 1 0 RAM2 RAM1 RAM0 0 0 0 R/W R/W R/W Flash Memory Area Selection When the RAMS bit is set to 1, these bits specify one of the following flash memory areas to be overlapped with part of RAM. 000: H'00000000 to H'00000FFF (EB0) 001: H'00001000 to H'00001FFF (EB1) 010: H'00002000 to H'00002FFF (EB2) 011: H'00003000 to H'00003FFF (EB3) 100: H'00004000 to H'00004FFF (EB4) 101: H'00005000 to H'00005FFF (EB5) 110: H'00006000 to H'00006FFF (EB6) 111: H'00007000 to H'00007FFF (EB7) Rev. 4.00 Dec 05, 2005 page 469 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) 18.6 On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the MD pin settings and FWP pin setting, as shown in table 18.3. When changing to boot mode, the boot program built into this LSI is initiated. The boot program transfers the programming control program from the externally-connected host to on-chip RAM via SCI3. After erasing the entire flash memory, the programming control program is executed. This can be used for programming initial values in the on-board state or for a forcible return when programming/erasing can no longer be done in user program mode. In user program mode, individual blocks can be erased and programmed by branching to the user program/erase control program prepared by the user. Table 18.3 Setting On-Board Programming Modes MD1 0 1 Note: * MD0 0 1 0 1 This LSI does not support this mode. User program mode FWP 0 LSI State after Reset End Boot mode Expanded mode* Single-chip mode Expanded mode* Single-chip mode Rev. 4.00 Dec 05, 2005 page 470 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) 18.6.1 Boot Mode Table 18.4 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 18.8, Flash Memory Programming/Erasing. 2. The SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be pulled up on the board if necessary. 4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the completion of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could not be performed normally, initiate boot mode again by a reset. Depending on the host's transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit rate and system clock frequency of this LSI within the ranges listed in table 18.5. 5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'FFFFD800 to H'FFFFFFFF is the area to which the programming control program is transferred from the host. The boot program area cannot be used until the execution state in boot mode switches to the programming control program. 6. Before branching to the programming control program, the chip terminates transfer operations by SCI3 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value remains set in BRR. Therefore, the programming control program can still use it for transfer of write data or verify data with the host. The TxD pin is high. The contents of the CPU general registers are undefined immediately after branching to the programming control program. These registers must be initialized at the beginning of the programming control program, as the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc. 7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at least 20 states, and then setting the mode (MD) pins. Boot mode is also cleared when a WDT overflow reset occurs. 8. 9. Do not change the MD pin input levels in boot mode. All interrupts are disabled during programming or erasing of the flash memory. Rev. 4.00 Dec 05, 2005 page 471 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) Table 18.4 Boot Mode Operation Host Operation Item Boot mode start Processing Contents Communications Contents LSI Operation Processing Contents Branches to boot program at reset-start. Boot program initiation Bit rate adjustment Continuously transmits data H'00 at specified bit rate. H'00, H'00 ...... H'00 Transmits data H'55 when data H'00 is received error-free. Receives data H'AA. Transfer of programming control program Transmits number of bytes (N) of programming control program to be transferred as 2-byte data (lower byte following upper byte) Transmits 1-byte of programming control program (repeated for N times) Flash memory erase H'00 H'55 H'AA * Measures low-level period of receive data H'00. * Calculates bit rate and sets it in BRR of SCI3. * Transmits data H'00 to host as adjustment end indication. Transmits data H'AA to host when data H'55 is received. Upper byte and lower byte Echoback H'XX Echoback Echobacks the 2-byte data received to host. Echobacks received data to host and also transfers it to RAM (repeated for N times) Boot program erase error Receives data H'AA. H'FF H'AA Checks flash memory data, erases all flash memory blocks in case of written data existing, and transmits data H'AA to host. (If erase could not be done, transmits data H'FF to host and aborts operation.) Branches to programming control program transferred to on-chip RAM and starts execution. Table 18.5 Peripheral Clock (P) Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate 9,600 bps 19,200 bps Peripheral Clock Frequency Range of LSI 4 to 40 MHz 8 to 40 MHz Rev. 4.00 Dec 05, 2005 page 472 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) 18.6.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program that provides the user program/erase control program from external memory. As the flash memory itself cannot be read during programming/erasing, transfer the user program/erase control program to on-chip RAM or external memory. Figure 18.6 shows a sample procedure for programming/erasing in user program mode. Prepare a user program/erase control program in accordance with the description in section 18.8, Flash Memory Programming/Erasing. Reset-start Program/erase? Yes Transfer user program/erase control program to RAM Branch to user program/erase control program in RAM No Branch to flash memory application program FWP = low* Execute user program/erase control program (flash memory rewrite) FWP = high Branch to flash memory application program Note: * Do not constantly apply a low level to the FWP pin. Only apply a low level to the FWP pin when programming or erasing the flash memory. To prevent excessive programming or excessive erasing, while a low level is being applied to the FWP pin, activate the watchdog timer in case of handling CPU runaways. Figure 18.6 Programming/Erasing Flowchart Example in User Program Mode Rev. 4.00 Dec 05, 2005 page 473 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) 18.7 Flash Memory Emulation in RAM A setting in the RAM emulation register (RAMER) enables part of RAM to overlap with the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. Emulation can be performed in user mode or user program mode. Figure 18.7 shows an example of emulation of real-time flash memory programming. 1. Set RAMER to overlap part of RAM with the area for which real-time programming is required. 2. Emulation is performed using the overlapped RAM. 3. After the program data has been confirmed, the RAMS bit is cleared, thus releasing the RAM overlap. 4. The data written in the overlapped RAM is written into the flash memory area. Start of emulation program Set RAMER Write tuning data to overlapped RAM Execute application program No Tuning OK? Yes Clear RAMER Write to flash memory emulation block End of emulation program Figure 18.7 Flowchart for Flash Memory Emulation in RAM Rev. 4.00 Dec 05, 2005 page 474 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) Figure 18.8 shows a sample procedure for flash memory block area overlapping. 1. The RAM area to be overlapped is fixed at a 4-kbyte area in the range H'FFFFD000 to H'FFFFDFFF. 2. The flash memory area to be overlapped is selected by RAMER from a 4-kbyte area of the EB0 to EB7 blocks. 3. The overlapped RAM area can be accessed from both the flash memory addresses and RAM addresses. 4. When the RAMS bit in RAMER is set to 1, program/erase protection is enabled for all flash memory blocks (emulation protection). In this state, setting the P or E bit in FLMCR1 to 1 does not cause a transition to program mode or erase mode. 5. A RAM area cannot be erased by execution of software in accordance with the erase algorithm. 6. Block area EB0 contains the vector table. When performing RAM emulation, the vector table is needed in the overlapped RAM. This area can be accessed from both the flash memory addresses and RAM addresses. H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 H'FFFFD000 Flash Memory EB8 to EB11 H'3FFFF On-chip RAM H'FFFFFFFF H'FFFFDFFF EB0 EB1 EB2 EB3 EB4 EB5 EB6 EB7 Figure 18.8 Example of RAM Overlap Operation (RAM[2:0] = b'000) Rev. 4.00 Dec 05, 2005 page 475 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) 18.8 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase the flash memory in onboard programming modes. Depending on the FLMCR1 and FLMCR2 settings, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing. Flash memory programming and erasing should be performed in accordance with the descriptions in section 18.8.1, Program/Program-Verify Mode and section 18.8.2, Erase/Erase-Verify Mode, respectively. 18.8.1 Program/Program-Verify Mode When writing data or programs to the flash memory, the program/program-verify flowchart shown in Figure 18.9 should be followed. Performing programming operations according to this flowchart will enable data or programs to be written to the flash memory without subjecting the chip to voltage stress or sacrificing program data reliability. 1. Programming must be done to an empty address. Do not reprogram an address to which programming has already been performed. 2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. 3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform reprogramming data computation and additional programming data computation according to Figure 18.9. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80. 5. The time during which the P bit is set to 1 is the programming time. Figure 18.9 shows the allowable programming time. 6. The watchdog timer (WDT) is set to prevent over programming due to program runaway, etc. An overflow cycle of approximately 6.6 ms is allowed. 7. For a dummy write to a verify address, write 1-byte data H'FF to an address to be read. Verify data can be read in longwords from the address to which a dummy write was performed. 8. The number of repetitions of the program/program-verify sequence to the same bit should not exceed the maximum number of programming (N). Rev. 4.00 Dec 05, 2005 page 476 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) Write pulse application subroutine Apply Write Pulse Enable WDT Set PSU bit in FLMCR1 Wait (tspsu) s Set P bit in FLMCR1 Wait (tsp10, tsp30, or tsp200) s Clear P bit in FLMCR1 Wait (tcp) s Clear PSU bit in FLMCR1 *7 Start of programming Start of programming START Set SWE bit in FLMCR1 Wait (tsswe) s Store 128-byte program data in program data area and reprogram data area n=1 m=0 Successively write 128-byte data from reprogram data area in RAM to flash memory Sub-Routine-Call Apply Write Pulse (tsp30 or tsp200) Set PV bit in FLMCR1 *7 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses. *4 *5 *7 End of programming *1 *7 See note *6 for pulse width Wait (tcpsu) s Disable WDT *7 Wait (tspv) s H'FF dummy write to verify address Wait (tspvr) s Read verify data Increment address Write data = verify data? OK 6n? NG NG *7 nn+1 *7 *2 *2 End Sub Note *6. Write Pulse Width Number of Writes n 1 2 3 4 5 6 7 8 9 10 11 12 13 Write Time (tsp) s tsp30 tsp30 tsp30 tsp30 tsp30 tsp30 tsp200 tsp200 tsp200 tsp200 tsp200 tsp200 tsp200 m=1 OK Additional-programming data computation Transfer additional-programming data to additional-programming data area *4 Reprogram data computation Transfer reprogram data to reprogram data area 128-byte data verification completed? OK Clear PV bit in FLMCR1 Wait (tcpv) s 6 n? NG *3 *4 998 999 1000 tsp200 tsp200 tsp200 NG * Use a tsp10 write pulse for additional programming. RAM Program data storage area (128 bytes) *7 Reprogram Reprogram data storage area (128 bytes) Additional-programming data storage area (128 bytes) OK Successively write 128-byte data from additionalprogramming data area in RAM to flash memory Sub-Routine-Call Apply Write Pulse (tsp10) (Additional programming) *1 *7 m = 0? OK Clear SWE bit in FLMCR1 NG n N? OK Clear SWE bit in FLMCR1 NG Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the start address to be written to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing fewer than 128 bytes; Wait (tcswe) s Wait (tcswe) s in this case, H'FF data must be written to the extra addresses. 2. Verify data is read in 32-bit (longword) units. Programming failure End of programming 3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to programming once again if the subsequent verify operation ends in failure. 4. A 128-byte area for the storage of programming data, a 128-byte area for the storage of reprogramming data, and a 128-byte area for the storage of additionalprogramming data must be provided in RAM. The contents of the reprogram data area and additional-program data area are modified as programming proceeds. 5. A write pulse of 30 s or 200 s is applied according to the progress of the programming operation. See note *6 for details of the pulse widths. When writing of additional-programming data is executed, a 10 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied. 7. The wait times and value of N are shown in section 22.5, Flash Memory characteristics. Reprogram Data Computation Table Original Data Verify Data Reprogram Data Comments (D) (V) (X) 1 Programming completed 0 0 0 Programming incomplete; reprogram 0 1 1 1 0 1 Still in erased state; no action 1 1 Additional-Programming Data Computation Table Reprogram Data (X') 0 0 1 1 Verify Data (V) 0 1 0 1 AdditionalProgramming Data (Y) 0 1 1 1 Comments *7 Additional programming to be executed Additional programming not to be executed Additional programming not to be executed Additional programming not to be executed Figure 18.9 Program/Program-Verify Flowchart Rev. 4.00 Dec 05, 2005 page 477 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) 18.8.2 Erase/Erase-Verify Mode When erasing flash memory, the erase/erase-verify flowchart shown in figure 18.10 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register 1 (EBR1) and the erase block register 2 (EBR2). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An overflow cycle of approximately 18.8 ms is allowed. 5. For a dummy write to a verify address, write 1-byte data H'FF to the read address. Verify data can be read in longwords from the address to which a dummy write was performed. 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The number of repetitions of the erase/erase-verify sequence should not exceed the maximum number of erasing (N). 18.8.3 Interrupt Handling when Programming/Erasing Flash Memory All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed or erased, or while the boot program is executing, for the following three reasons: 1. An interrupt during programming/erasing may cause a violation of the programming or erasing algorithm, with the result that normal operation cannot be assured. 2. If an interrupt exception handling starts before the vector address is written or during programming/erasing, a correct vector cannot be fetched and the CPU malfunctions. 3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be carried out. Rev. 4.00 Dec 05, 2005 page 478 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) Erase start SWE bit 1 Wait (tSSWE) s n1 *1 Set EBR1 and EBR2 Enable WDT ESU bit 1 Wait (tSESU) E bit 1 Wait (tSE) E bit 0 Wait (tCE) ESU bit 0 Wait (tCESU) Disable WDT EV bit 1 Wait (tSEV) Set block start address as verify address *3 H'FF dummy write to verify address Wait (tSEVR) Read verify data *2 No nn+1 Increment address Verify data = all 1s? Yes No Last address of block? Yes EV bit 0 Wait (tCEV) No *4 All erase block erased? Yes SWE bit 0 Wait (tCSWE) End of erasing EV bit 0 Wait (tCEV) n N? No Yes SWE bit 0 Wait (tCSWE) Erase failure Notes: 1. 2. 3. 4. Prewriting (setting erase block data to all 0s) is not necessary. Verify data is read in 32-bit (longword) units. Make only a single-bit specification in the erase block register 1 (EBR1) and the erase block register 2 (EBR2). Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn. Figure 18.10 Erase/Erase-Verify Flowchart Rev. 4.00 Dec 05, 2005 page 479 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) 18.9 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 18.9.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Flash memory control register 1 (FLMCR1), flash memory control register 2 (FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2) are initialized Protect Function Item FWP pin protect Description Program Erase Yes When a high level is input to the FWP pin, FLMCR1, Yes EBR 1, and EBR 2 are initialized, and the program/erase protection state is entered. In the reset state (including the reset state when the Yes WDT overflows) and standby mode, FLMCR1, EBR 1, and EBR 2 are initialized, and the program/erase protection state is entered. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the AC Characteristics section. Reset/standby protect Yes 18.9.2 Software Protection Software protection can be implemented against programming/erasing of all flash memory blocks by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase block register 1 (EBR1), erase protection can be set for individual blocks. When EBR1 is set to H'00, erase protection is set for all blocks. Rev. 4.00 Dec 05, 2005 page 480 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) Protect Function Item SWE bit protect Description When the SWE bit in FLMCR1 is cleared to 0, all blocks are program/erase-protected. (This setting should be carried out in on-chip RAM.) By setting the erase block register 1 (EBR1) and the erase block register 2 (EBR2), erase protection can be set for individual blocks. When both EBR1 and EBR2 are set to H'00, erase protection is set for all blocks. Emulation protect When the RAMS bit in RAMER is set to 1, all blocks are program/erase-protected. Yes Yes Program Yes Erase Yes Block protect Yes 18.9.3 Error Protection In error protection, an error is detected when CPU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is forcibly aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. When the following errors are detected during programming/erasing of flash memory, the FLER bit in FLMCR2 is set to 1, and the error protection state is entered. * When the flash memory is read during programming/erasing (including vector read and instruction fetch) * Immediately after exception handling (excluding a reset) during programming/erasing * When a SLEEP instruction is executed during programming/erasing The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, however program mode or erase mode is forcibly aborted at the point when the error is detected. Program mode or erase mode cannot be re-entered by re-setting the P or E bit. However, PV and EV bit settings are retained, and a transition can be made to verify mode. The error protection state can be cancelled by the power-on reset only. Rev. 4.00 Dec 05, 2005 page 481 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) 18.10 PROM Programmer Mode In PROM programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as for a discrete flash memory. Use a PROM programmer that supports the Renesas 256-kbyte flash memory on-chip MCU device type (FZTAT256V3A). 18.11 Usage Note * Setting module standby mode For flash memory, this module can be disabled/enabled by the module standby control register. Flash memory operation is enabled for the initial value. Accessing flash memory is disabled by setting module standby mode. For more information, see section 21, Power-Down Modes. 18.12 Notes when Converting the F-ZTAT Versions to the Mask-ROM Versions Please note the following when converting the F-ZTAT versions to the mask-ROM versions, with using the F-ZTAT application software. In the mask-ROM version, addresses of the flash memory registers (refer to appendix A.1, Register Addresses (Order of Address)) return undefined value if read. When the F-ZTAT application software is used in the mask-ROM versions, the FWP pin level cannot be determined. When converting the program, make sure the reprogramming (erasing/programming) part of the flash memory and the RAM emulation part not to be initiated. In the mask-ROM versions, boot mode pin setting should not be performed. Note: This difference applies to all the F-ZTAT versions and all the mask-ROM versions that have different ROM size. Rev. 4.00 Dec 05, 2005 page 482 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) 18.13 Notes on Flash Memory Programming and Erasing Precautions concerning the use of on-board programming mode, the RAM emulation function, and programmer mode are summarized below. Use the specified voltages and timing for programming and erasing: Appling excessive voltage beyond the specification can permanently damage the device. Use an EPROM programmer that supports the Renesas' microcomputer device having on-chip 256-kbyte flash memory. Use only the specified socket adapter, otherwise a serious damage may occur. Powering on and off (see figures 18.11 to 18.13): Do not apply a low level to the FWP pin until VCC has been stabilized. Also, drive the FWP pin high before turning off VCC. If VCC is to be applied or disconnected, fix the FWP pin level at VCC and place the flash memory in the hardware protection state in advance. Conditions for this power-on and power-off timing should also be applied in the event of a power failure and subsequent recovery. FWP application/disconnection (see figures 18.11 to 18.13): If VCC is on or off while low level is applied to FWP pin, a voltage surge from low level on the RESET pin may cause unintentional programming or erasing of flash memory. Applying voltage to FWP should be carried out while MCU operation is in a stable condition. If MCU operation is not stable, fix the FWP pin high and set the protection state. The following points must be observed concerning FWP application and disconnection to prevent unintentional programming or erasing of flash memory: * Apply voltage to FWP while the VCC voltage is stable enough to satisfy the specification voltage range. * In boot mode, apply voltage to FWP or disconnect it during a reset. * Prior to applying voltage while FWP pin is in low level in boot mode, ensure that the RESET pin level is surely kept low despite the applying voltage is rising to VCC. Note that in a case where ICs for reset are used, the voltage level of RESET pin can transiently exceed 1/2 VCC while VCC is rising. * In user program mode, FWP can be switched between high and low level regardless of the reset state. FWP input can also be switched during execution of a program in flash memory. * Apply voltage to FWP while programs are not running away. * Disconnect FWP only when the SWE, ESU, PSU, EV, PV, P, and E bits in FLMCR1 are cleared. Make sure that the SWE, ESU, PSU, EV, PV, P, and E bits are not set by mistake when applying voltage to FWP pin or disconnecting. Do not apply a constant low level to the FWP pin: If a program runs away while low level is applied to FWP pin, incorrect programming or erasing may occur. Apply a low level to the FWP Rev. 4.00 Dec 05, 2005 page 483 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) pin only when programming or erasing flash memory. Avoid creating a system configuration in which a low level is constantly applied to the FWP pin. Also, while a low level is applied to the FWP pin, the watchdog timer should be activated to prevent excess programming or excess erasing due to program runaway, etc. Use the recommended algorithm when programming and erasing flash memory: The recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. When setting the P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. Do not set or clear the SWE bit during execution of a program in flash memory: Wait for at least 100 s after clearing the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten. Access flash memory only for verify operations (verification during programming/erasing). Also, do not clear the SWE bit during programming, erasing, or verifying. Similarly, when using the RAM emulation function while a low level is being input to the FWP pin, the SWE bit must be cleared before executing a program or reading data in flash memory. However, the RAM area overlapping flash memory space can be read and written to regardless of whether the SWE bit is set or cleared. Do not use interrupts while flash memory is being programmed or erased: All interrupt requests, including NMI, should be disabled during FWP application to give priority to program/erase operations. Do not perform additional programming. Erase the memory before reprogramming: In onboard programming, perform only one programming operation on a 128-byte programming unit block. In programmer mode, too, perform only one programming operation on a 128-byte programming unit block. Programming should be carried out with the entire programming unit block erased. Before programming, check that the chip is correctly mounted in the EPROM programmer: Overcurrent damage to the device can result if the index marks on the EPROM programmer socket, socket adapter, and chip are not correctly aligned. Do not touch the socket adapter or chip during programming: Casual contact with either of these by hand or something while programming can generate a transient noise on the FWP and RESET pins or cause incorrect programming or erasing due to bad electrical contact. Reset the flash memory before turning on the power: If VCC is applied to the RESET pin while in high state, mode signals are not correctly downloaded, causing MCU's runaway. In a case where FWP pin is in low state, incorrect programming or erasing can occur. Rev. 4.00 Dec 05, 2005 page 484 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) Apply the reset signal while SWE is low to reset the flash memory during its operation: The reset signal is applied at least 100 s after the SWE bit has been cleard. Comply with power-on procedure designated by the programmer maker: When executing an on-board writing with a programmer, incorrect programming or erasing may occur unless the power-on procedure designated by the programmer makers is applied. Wait time: tsswe Programming/erasing possible Wait time: 100 s CK tosc1 min 0 s Vcc *3 tMDS min 0 s FWP MD3 to MD0*1 tMDS*3 RES SWE set SWE bit Period during which flash memory access is prohibited (tsswe: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program if flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD3 to MD0) must be fixed until power-off by pulling the pins up or down. 2. See Section 22.5, Flash Memory Characteristics in Electrical Characteristics. 3. See Section 22.3.3, Control Signal Timing in Electrical Characteristics. SWE cleared Figure 18.11 Power-On/Off Timing (Boot Mode) Rev. 4.00 Dec 05, 2005 page 485 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) Wait time: tsswe Programming/erasing possible Wait time: 100 s CK tosc1 min 0 s Vcc FWP MD3 to MD0*1 *3 tMDS RES SWE set SWE bit Period during which flash memory access is prohibited (tsswe: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program if flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. Except when switching modes, the level of the mode pins (MD3 to MD0) must be fixed until power-off by pulling the pins up or down. 2. See Section 22.5, Flash Memory Characteristics in Electrical Characteristics. 3. See Section 22.3.3, Control Signal Timing in Electrical Characteristics. SWE cleared Figure 18.12 Power-On/Off Timing (User Program Mode) Rev. 4.00 Dec 05, 2005 page 486 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) Programming/erasing possible Wait time: tsswe Programming/erasing possible Wait time: tsswe Programming/erasing possible *4 *4 *4 Wait time: tsswe Programming/erasing possible *4 User mode User program mode CK tosc1 Vcc * tMDS 2 Wait time: tsswe min 0 s FWP * tMDS 2 MD3 to MD0 * tMDS 2 tRESW RES SWE set SWE bit SWE cleared Mode change *1 Boot mode Mode 1 User change* mode User program mode Period during which flash memory access is prohibited (tsswe: Wait time after setting SWE bit)*3 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1. When entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of RES input. 2. See Section 22.3.3, Control Signal Timing in Electrical Characteristics. 3. See Section 22.5, Flash Memory Characteristics in Electrical Characteristics. 4. Wait time: 100 s. Figure 18.13 Mode Transition Timing (Example: Boot Mode User Mode User Program Mode) Rev. 4.00 Dec 05, 2005 page 487 of 564 REJ09B0270-0400 Section 18 Flash Memory (F-ZTAT Version) Rev. 4.00 Dec 05, 2005 page 488 of 564 REJ09B0270-0400 Section 19 Mask ROM Section 19 Mask ROM This LSI is available with 64 kbytes or 128 kbytes of on-chip ROM. The on-chip ROM is connected to the CPU and data transfer controller (DTC) through a 32-bit data bus (figures 19.1 and 19.2). The CPU and DTC can access the on-chip ROM in 8, 16 and 32-bit widths. Data in the on-chip ROM can always be accessed in one cycle. Internal data bus (32 bits) H'00000000 H'00000004 H'00000001 H'00000005 H'00000002 H'00000006 H'00000003 H'00000007 On-chip ROM H'0000FFFC H'0000FFFD H'0000FFFE H'0000FFFF Figure 19.1 Mask ROM Block Diagram (SH7148) Internal data bus (32 bits) H'00000000 H'00000004 H'00000001 H'00000005 H'00000002 H'00000006 H'00000003 H'00000007 On-chip ROM H'0001FFFC H'0001FFFD H'0001FFFE H'0001FFFF Figure 19.2 Mask ROM Block Diagram (SH7048) Rev. 4.00 Dec 05, 2005 page 489 of 564 REJ09B0270-0400 Section 19 Mask ROM The operating mode determines whether the on-chip ROM is valid or not. The operating mode is selected using mode-setting pins FWP and MD3 to MD0 as shown in table 3.1. Only the mode 3 is supported in this LSI. The on-chip ROM is allocated to addresses H'00000000 to H'0000FFFF of memory area 0 (SH7148), H'00000000 to H'0001FFFF of memory area 0 (SH7048). 19.1 Usage Note * Setting module standby mode For mask ROM, this module can be disabled/enabled by the module standby control register. Mask ROM operation is enabled for the initial value. Accessing mask ROM is disabled by setting module standby mode. For more information, see section 21, Power-Down Modes. Rev. 4.00 Dec 05, 2005 page 490 of 564 REJ09B0270-0400 Section 20 RAM Section 20 RAM The SH7046 Group has an on-chip high-speed static RAM. The on-chip RAM is connected to the CPU, data transfer controller (DTC) by a 32-bit data bus, enabling 8, 16, or 32-bit width access to data in the on-chip RAM. Data in the on-chip RAM can always be accessed in one cycle, providing high-speed access that makes this RAM ideal for use as a program area, stack area, or data area. The contents of the on-chip RAM are retained in both sleep and software standby modes. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on the system control register (SYSCR), refer to section 21.2.2, System Control Register (SYSCR). Product Type SH7046 Type of ROM Flash memory Mask ROM RAM Capacity 12 kbytes 4 kbytes RAM Address H'FFFFD000 to H'FFFFFFFF H'FFFFF000 to H'FFFFFFFF 20.1 Usage Note * Module Standby Mode Setting RAM can be enabled/disabled by the module standby control register. The initial value enables RAM operation. RAM access is disabled by setting the module standby mode. For details, see section 21, Power-Down Modes. Rev. 4.00 Dec 05, 2005 page 491 of 564 REJ09B0270-0400 Section 20 RAM Rev. 4.00 Dec 05, 2005 page 492 of 564 REJ09B0270-0400 Section 21 Power-Down Modes Section 21 Power-Down Modes In addition to the normal program execution state, this LSI has four power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip peripheral functions, and so on. This LSI's power-down modes are as follows: (1) Sleep mode (2) Software standby mode (3) Module standby mode Sleep mode indicates the state of the CPU, and module standby mode indicates the state of the onchip peripheral function (including the bus master other than the CPU). Some of these states can be combined. After a reset, the LSI is in normal-operation mode. Table 21.1 lists internal operation states in each mode. Rev. 4.00 Dec 05, 2005 page 493 of 564 REJ09B0270-0400 Section 21 Power-Down Modes Table 21.1 Internal Operation States in Each Mode Function System clock pulse generator CPU External interrupts Peripheral functions Instructions Registers NMI IRQ3 to IRQ0 UBC DTC I/O port WDT SCI A/D MTU CMT MMT ROM RAM Functioning Functioning Functioning Functioning Halted (reset) Retained Halted (reset) Retained Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Halted (reset) Halted (reset) Functioning Functioning Halted (reset) Halted (retained) Halted (reset) Retained Halted (retained) Halted (reset) Functioning Normal operation Functioning Functioning Sleep Functioning Halted (retained) Functioning Module Standby Functioning Functioning Functioning Software Standby Halted Halted (retained) Functioning Notes: 1. "Halted (retained)" means that the operation of the internal state is suspended, although internal register values are retained. 2. "Halted (reset)" means that internal register values and internal state are initialized. 3. In module standby mode, only modules for which a stop setting has been made are halted (reset or retained). 4. There are two types of on-chip peripheral module registers; ones which are initialized in software standby mode and module standby mode, and those not initialized those modes. For details, refer to appendix A.3, Register States in Each Operating Mode. 5. The port high-impedance bit (HIZ) in SBYCR sets the state of the I/O port in software standby mode. For details on the setting, refer to section 21.2.1, Standby Control Register (SBYCR). For the state of pins, refer to appendix B, Pin States. Rev. 4.00 Dec 05, 2005 page 494 of 564 REJ09B0270-0400 Section 21 Power-Down Modes Reset state RES pin = High Program execution state SLEEP instruction Program-halted state SSBY = 0 Sleep mode (main clock) Normal-operation mode (main clock) SLEEP instruction External interrupt* SSBY = 1 Software standby mode : Transition after exception processing : Power-down mode Notes: * NMI and IRQ * When a transition is made between modes by means of an interrupt, the transition cannot be made on interrupt source generation alone. Ensure that interrupt handling is performed after accepting the interrupt request. * A transition to the reset state occurs when RES is driven low. Figure 21.1 Mode Transition Diagram Rev. 4.00 Dec 05, 2005 page 495 of 564 REJ09B0270-0400 Section 21 Power-Down Modes 21.1 Input/Output Pins Table 21.2 lists the pins relating to power-down mode. Table 21.2 Pin Configuration Pin Name RES MRES I/O Input Input Function Power-on reset input pin Manual reset input pin 21.2 Register Descriptions Registers related to power down modes are shown below. For details on register addresses and register states during each process, refer to appendix A, Internal I/O Register. * Standby control register (SBYCR) * System control register (SYSCR) * Module standby control register 1 (MSTCR1) * Module standby control register 2 (MSTCR2) 21.2.1 Standby Control Register (SBYCR) SBYCR is an 8-bit readable/writable register that performs software standby mode control. Bit 7 Bit Name SSBY Initial Value 0 R/W R/W Description Software Standby This bit specifies the transition mode after executing the SLEEP instruction. 0: Shifts to sleep mode after the SLEEP instruction has been executed 1: Shifts to software standby mode after the SLEEP instruction has been executed This bit cannot be set to 1 when the watchdog timer (WDT) is operating (when the TME bit in TCSR of the WDT is set to 1). When transferring to software standby mode, clear the TME bit to 0, stop the WDT, then set the SSBY bit to 1. Rev. 4.00 Dec 05, 2005 page 496 of 564 REJ09B0270-0400 Section 21 Power-Down Modes Initial Value 0 Bit 6 Bit Name HIZ R/W R/W Description Port High-Impedance In software standby mode, this bit selects whether the pin state of the I/O port is retained or changed to highimpedance. 0: In software standby mode, the pin state is retained. 1: In software standby mode, the pin state is changed to high-impedance. The HIZ bit cannot be set to 1 when the TEM bit in TCSR of the WDT is set to 1. When changing the pin state of the I/O port to highimpedance, clear the TEM bit to 0, then set the HIZ bit to 1. 5 0 R Reserved This bit is always read as 0, and should always be written with 0. 4 to 1 All 1 R Reserved These bits are always read as 1, and should always be written with 1. 0 IRQEL 1 R/W IRQ3 to IRQ0 Enable IRQ interrupts are enabled to clear software standby mode. 0: Software standby mode is cleared. 1: Software standby mode is not cleared. Rev. 4.00 Dec 05, 2005 page 497 of 564 REJ09B0270-0400 Section 21 Power-Down Modes 21.2.2 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that performs enables/disables the access to the onchip RAM. Bit 7, 6 Bit Name Initial Value All 1 R/W R/W Description Reserved These bits are always read as 1, and should always be written with 1. 5 to 1 All 0 R Reserved These bits are always read as 0, and should always be written with 0. 0 RAME 1 R/W RAM Enable This bit enables/disables the on-chip RAM. 0: On-chip RAM disabled 1: On-chip RAM enabled When this bit is cleared to 0, the access to the on-chip RAM is disabled. In this case, an undefined value is returned when reading or fetching the data or instruction from the on-chip RAM, and writing to the on-chip RAM is ignored. When RAME is cleared to 0 to disable the on-chip RAM, an instruction to access the on-chip RAM should not be set next to the instruction to write to SYSCR. If such an instruction is set, normal access is not guaranteed. When RAME is set to 1 to enable the on-chip RAM, an instruction to read SYSCR should be set next to the instruction to write to SYSCR. If an instruction to access the on-chip RAM is set next to the instruction to write to SYSCR, normal access is not guaranteed. Rev. 4.00 Dec 05, 2005 page 498 of 564 REJ09B0270-0400 Section 21 Power-Down Modes 21.2.3 Module Standby Control Registers 1 and 2 (MSTCR1 and MSTCR2) MSTCR, comprising two 16-bit readable/writable registers, performs module standby mode control. Setting a bit to 1, the corresponding module enters module standby mode, while clearing the bit to 0 clears the module standby mode. MSTCR1 Bit Initial Bit Name Value All 1 R/W R/W Description Reserved These bits are always read as 1, and should always be written with 1. 11 10 9 8 MSTP27 MSTP26 MSTP25 MSTP24 0 0 0 0 R/W R/W R/W R/W On-chip RAM On-chip ROM Data transfer controller (DTC) Set the identical value to MSTP25 and MSTP24, respectively. When setting module standby, write b'11, while clearing, write b'00. Reserved These bits are always read as 0, and should always be written with 0. 5, 4 All 1 R/W Reserved These bits are always read as 1, and should always be written with 1. 3 2 1, 0 MSTP19 MSTP18 1 1 All 1 R/W R/W R/W Serial communication interface 3 (SCI_3) Serial communication interface 2 (SCI_2) Reserved These bits are always read as 1, and should always be written with 1 15 to 12 7, 6 All 0 R Rev. 4.00 Dec 05, 2005 page 499 of 564 REJ09B0270-0400 Section 21 Power-Down Modes MSTCR2 Bit 15 Bit Name Initial Value 1 R/W R/W Description Reserved This bit is always read as 1, and should always be written with 1. 14 13 12 11 10 9, 8 MSTP14 MSTP13 MSTP12 1 1 1 0 0 All 0 R/W R/W R/W R R/W R/W Motor management timer (MMT) Multi-function timer pulse unit (MTU) Compare match timer (CMT) Reserved These bits are always read as 0, and should always be written with 0. Reserved These bits are always read as 0, and should always be written with 0. 7 1 R/W Reserved This bit is always read as 1, and should always be written with 1. 6 5 4 3 to 1 MSTP6 MSTP5 MSTP4 1 1 1 All 0 R/W R/W R/W R A/D converter (A/D2) A/D converter (A/D1) A/D converter (A/D0) Reserved These bits are always read as 0, and should always be written with 0. 0 MSTP0 0 R/W User break controller (UBC) Rev. 4.00 Dec 05, 2005 page 500 of 564 REJ09B0270-0400 Section 21 Power-Down Modes 21.3 21.3.1 Operation Sleep Mode Transition to Sleep Mode: If SLEEP instruction is executed while the SSBY bit in SBYCR = 0, the CPU enters sleep mode. In sleep mode, CPU operation stops, however the contents of the CPU's internal registers are retained. Peripheral functions except the CPU do not stop. In sleep mode, data should not be accessed by the DTC. Clearing Sleep Mode: Sleep mode is cleared by the conditions below. * Clearing by the power-on reset When the RES pin is driven low, the CPU enters the reset state. When the RES pin is driven high after the elapse of the specified reset input period, the CPU starts the reset exception handling. When an internal power-on reset by the WDT occurs, sleep mode is also cleared. * Clearing by the manual reset When the MRES pin is driven low while the RES pin is high, the CPU shifts to the manual reset state and thus sleep mode is cleared. When an internal manual reset by the WDT occurs, sleep mode is also cleared. 21.3.2 Software Standby Mode Transition to Software Standby Mode: A transition is made to software standby mode if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1. In this mode, the CPU, on-chip peripheral functions, and the oscillator, all stop. However, the contents of the CPU's internal registers and on-chip RAM data are retained as long as the specified voltage is supplied. There are two types of on-chip peripheral module registers; ones which are initialized by software standby mode, and those not initialized by that mode. For details, refer to appendix A.3, Register States in Each Operating Mode. The port high-impedance bit (HIZ) in SBYCR sets the state of the I/O port either to "retained" or "high-impedance". For the state of pins, refer to appendix B, Pin States. In software standby mode, the oscillator stops and thus power consumption is significantly reduced. Rev. 4.00 Dec 05, 2005 page 501 of 564 REJ09B0270-0400 Section 21 Power-Down Modes Clearing Software Standby Mode: Software standby mode is cleared by the condition below. * Clearing by the NMI interrupt input When the falling edge or rising edge of the NMI pin (selected by the NMI edge select bit (NMIE) in ICR1 of the interrupt controller (INTC)) is detected, clock oscillation is started. This clock pulse is supplied only to the watchdog timer (WDT). After the elapse of the time set in the clock select bits (CKS2 to CKS0) in TCSR of the WDT before the transition to software standby mode, the WDT overflow occurs. Since this overflow indicates that the clock has been stabilized, clock pulse will be supplied to the entire chip after this overflow. Software standby mode is thus cleared and the NMI exception handling is started. When clearing software standby mode by the NMI interrupt, set CKS2 to CKS0 bits so that the WDT overflow period will be longer than the oscillation stabilization time. When software standby mode is cleared by the falling edge of the NMI pin, the NMI pin should be high when the CPU enters software standby mode (when the clock pulse stops) and should be low when the CPU returns from standby mode (when the clock is initiated after the oscillation stabilization). When software standby mode is cleared by the rising edge of the NMI pin, the NMI pin should be low when the CPU enters software standby mode (when the clock pulse stops) and should be high when the CPU returns from software standby mode (when the clock is initiated after the oscillation stabilization). * Clearing by the RES pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation is started, clock pulse is supplied to the entire chip. Ensure that the RES pin is held low until clock oscillation stabilizes. When the RES pin is driven high, the CPU starts the reset exception handling. * Clearing by the IRQ interrupt input When the IRQEL bit in the standby control register (SBYCR) is set to 1 and when the falling edge or rising edge of the IRQ pin (selected by the IRQ3S to IRQ0S bits in ICR1 of the interrupt controller (INTC) and the IRQ3ES[1:0] to IRQ0ES[1:0] bits in ICR2) is detected, clock oscillation is started.* This clock pulse is supplied only to the watchdog timer (WDT). The IRQ interrupt priority level should be higher than the interrupt mask level set in the status register (SR) of the CPU before the transition to software standby mode. After the elapse of the time set in the clock select bits (CKS2 to CKS0) in TCSR of the WDT before the transition to software standby mode, the WDT overflow occurs. Since this overflow indicates that the clock has been stabilized, clock pulse will be supplied to the entire chip after this overflow. Software standby mode is thus cleared and the IRQ exception handling is started. Rev. 4.00 Dec 05, 2005 page 502 of 564 REJ09B0270-0400 Section 21 Power-Down Modes When clearing software standby mode by the IRQ interrupt, set CKS2 to CKS0 bits so that the WDT overflow period will be longer than the oscillation stabilization time. When software standby mode is cleared by the falling edge or both edges of the IRQ pin, the IRQ pin should be high when the CPU enters software standby mode (when the clock pulse stops) and should be low when the CPU returns from software standby mode (when the clock is initiated after the oscillation stabilization). When software standby mode is cleared by the rising edge of the IRQ pin, the IRQ pin should be low when the CPU enters software standby mode (when the clock pulse stops) and should be high when the CPU returns from software standby mode (when the clock is initiated after the oscillation stabilization). Note: * When the IRQ pin is set to falling-edge detection or both-edge detection, clock oscillation starts at falling-edge detection. When the IRQ pin is set to rising-edge detection, clock oscillation starts at rising-edge detection. Do not set the IRQ pin to low-level detection. Software Standby Mode Application Example: Figure 21.2 shows an example in which a transition is made to software standby mode at the falling edge of the NMI pin, and software standby mode is cleared at a rising edge of the NMI pin. In this example, when the NMI pin is driven low while the NMI edge select bit (NMIE) in ICR1 is 0 (falling edge detection), an NMI interrupt is accepted. Then, the NMIE bit is set to 1 (rising edge detection) in the NMI exception service routine, the SSBY bit in SBYCR is set to 1, and a SLEEP instruction is executed to transfer to software standby mode. Software standby mode is cleared by driving the NMI pin from low to high. Rev. 4.00 Dec 05, 2005 page 503 of 564 REJ09B0270-0400 Section 21 Power-Down Modes Oscillator CK NMI input NMIE bit SSBY bit LSI state NMI Program exception execution state handling Exception service routine Software standby mode Oscillation WDT start time setting time Oscillation stabilization time NMI exception handling Figure 21.2 NMI Timing in Software Standby Mode 21.3.3 Module Standby Mode Module standby mode can be set for individual on-chip peripheral functions. When the corresponding MSTP bit in MSTCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module standby mode. The CPU continues operating independently. When the corresponding MSTP bit is cleared to 0, module standby mode is cleared and the module starts operating at the end of the bus cycle. In module standby mode, the internal states of modules are initialized. After reset clearing, the SCI, MTU, MMT, CMT, and A/D converter are in module standby mode. When an on-chip supporting module is in module standby mode, read/write access to its registers is disabled. Rev. 4.00 Dec 05, 2005 page 504 of 564 REJ09B0270-0400 Section 21 Power-Down Modes 21.4 21.4.1 Usage Notes I/O Port Status When a transition is mode to software standby mode while the port high-impedance bit (HIZ) in SBYCR is 0, I/O port states are retained. Therefore, there is no reduction in current consumption for the output current when a high-level signal is output. 21.4.2 Current Consumption during Oscillation Stabilization Wait Period Current consumption increases during the oscillation stabilization wait period. 21.4.3 On-Chip Peripheral Module Interrupt Relevant interrupt operations cannot be performed in module standby mode. Consequently, if the CPU enters module standby mode while an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering module standby mode. 21.4.4 Writing to MSTCR1 and MSTCR2 MSTCR1 and MSTCR2 should only be written to by the CPU. 21.4.5 DTC Operation in Sleep Mode In sleep mode, data should not be accessed by the DTC. Rev. 4.00 Dec 05, 2005 page 505 of 564 REJ09B0270-0400 Section 21 Power-Down Modes Rev. 4.00 Dec 05, 2005 page 506 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics Section 22 Electrical Characteristics 22.1 Absolute Maximum Ratings Table 22.1 shows the absolute maximum ratings. Table 22.1 Absolute Maximum Ratings Item Power supply voltage Input voltage EXTAL pins All pins other than analog input and EXTAL pins Analog supply voltage Analog input voltage Operating temperature (except writing or erasing flash memory) Standard product* Wide temperature-range product* TWEopr Tstg Symbol VCC Vin Vin AVCC VAN Topr Rating -0.3 to + 7.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to + 7.0 -0.3 to AVCC + 0.3 -20 to + 75 -40 to + 85 -20 to + 75 -55 to + 125 C C Unit V V V V V C Operating temperature (writing or erasing flash memory) Storage temperature [Operating precaution] Operating the LSI in excess of the absolute maximum ratings may result in permanent damage. Note: * See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. Rev. 4.00 Dec 05, 2005 page 507 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics 22.2 DC Characteristics Table 22.2 DC Characteristics Conditions: VCC = 4.0 to 5.5 V, AVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to 1 +75C (Standard product)* , Ta = -40C to +85C (Wide temperature-range 1 product)* . Item Input high-level RES, MRES, NMI, voltage (except FWP, MD3 to MD0 Schmitt trigger EXTAL input voltage) A/D port Other input pins Input low-level RES, MRES, NMI, voltage (except FWP, MD3 to MD0, Schmitt trigger EXTAL input voltage) Other input pins Schmitt trigger input voltage IRQ3 to IRQ0, POE6 to POE0, TCLKA to TCLKD, TIOC0A to TIOC0D, TIOC1A, TIOC1B, TIOC2A, TIOC2B, TIOC3A to TIOC3D, TIOC4A to TIOC4D RES, MRES, NMI, FWP, MD3 to MD0 Ports F and G Other input pins VIL Symbol VIH Min VCC - 0.7 VCC - 0.7 2.2 2.2 -0.3 Typ Max VCC + 0.3 VCC + 0.3 AVCC + 0.3 VCC + 0.3 0.5 Unit V V V V V Measurement Conditions -0.3 VT+ (VIH) VT- (VIL) VT+-VT- VCC - 0.5 -0.3 0.4 0.8 VCC + 0.3 1.0 V V V V Input leak current | Iin | 1.0 A Vin = 0.5 to VCC -0.5 V Vin = 0.5 to AVCC -0.5 V Vin = 0.5 to VCC -0.5 V 1.0 1.0 A A Rev. 4.00 Dec 05, 2005 page 508 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics Measurement Conditions Vin = 0.5 to VCC -0.5 V IOH = -200 A IOH = -1 mA IOL = 1.6 mA IOL = 15 mA Vin = 0 V = 1 MHz Ta = 25C NMI All other input pins Current consumption*2 Normal Clock 1:1 ICC operation Clock 1:1/2 Sleep Clock 1:1 Clock 1:1/2 Standby Analog supply current During A/D conversion, A/D converter idle state During standby RAM standby voltage VRAM AICC 130 160 110 110 1 3.0 50 20 160 180 130 130 10 50 5.0 pF pF mA mA mA mA A A mA = 40 MHz = 50 MHz = 40 MHz = 50 MHz Ta 50C 50C < Ta Item Three-state leak current (while OFF) Output highlevel voltage Output lowlevel voltage Input capacitance Ports A, B, and E Symbol | Itsi | Min Typ Max 1.0 Unit A All output pins VOH VCC - 0.5 3.5 0.4 1.5 80 V V V V pF All output pins PE9, PE11 to PE21 RES VOL Cin 2.0 5.0 A V VCC [Operating precaution] When the A/D converter is not used, do not leave the AVCC, and AVSS pins open. Notes: 1. See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. 2. The current consumption is measured when VIHmin = VCC - 0.5 V, VIL = 0.5 V, with all output pins unloaded. Rev. 4.00 Dec 05, 2005 page 509 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics Table 22.3 Permitted Output Current Values Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C 1 to +75C (Standard product)* , Ta = -40C to +85C (Wide temperature-range 1 product)* . Item Output low-level permissible current (per pin) Output low-level permissible current (total) Output high-level permissible current (per pin) Output high-level permissible current (total) Symbol IOL IOL -IOH -IOH Min Typ Max 2.0* 110 2.0 25 2 Unit mA mA mA mA [Operating precautions] To assure LSI reliability, do not exceed the output values listed in this table. Notes: 1. See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. 2. IOL= 15 mA (max) about the pins PE9, PE11 to PE21. However, three pins at most are permitted to have simultaneously IOL > 2.0 mA among these pins. Rev. 4.00 Dec 05, 2005 page 510 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics 22.3 22.3.1 AC Characteristics Test Conditions for the AC Characteristics high level: VIH minimum value, low level: VIL maximum value high level: 2.0 V, low level: 0.8 V IOL Input reference levels Output reference levels LSI output pin DUT output CL V VREF IOH CL is a total value that includes the capacitance of measurement equipment, and is set as follows: 30 pF: IRQOUT 30 pF: Port output pins and peripheral module output pins other than the above It is assumed that IOL = 1.6 mA, IOH = 200 A in the test conditions. Figure 22.1 Output Load Circuit Rev. 4.00 Dec 05, 2005 page 511 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics 22.3.2 Clock Timing Table 22.4 shows the clock timing. Table 22.4 Clock Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (Standard product)*, Ta = -40C to +85C (Wide temperature-range product)*. Item Operating frequency 50MHz operation* 40MHz operation* Clock cycle time 50MHz operation* 40MHz operation* Clock low-level pulse width Clock high-level pulse width Clock rise time Clock fall time EXTAL clock input frequency EXTAL clock input cycle time EXTAL clock input low-level pulse width EXTAL clock input high-level pulse width 50MHz operation* 40MHz operation* 50MHz operation* 40MHz operation* 50MHz operation* 40MHz operation* 50MHz operation* 40MHz operation* tEXH tEXL tCL tCH tCR tCF fEX tEXcyc Symbol fop tcyc Min 4 4 20 25 4 4 4 4 80 100 35 45 35 45 tEXR tEXF tOSC1 tOSC2 tpcyc 10 10 25 Max 50 40 250 250 5 5 12.5 10.0 250 250 5 5 500 ns ns ms ms ns Figure 22.4 ns ns ns ns ns ns ns MHz Figure 22.3 ns Unit MHz Figures Figure 22.2 EXTAL clock input rise time EXTAL clock input fall time Reset oscillation settling time Standby return oscillation settling time Clock cycle time for peripheral modules Note: * See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. Rev. 4.00 Dec 05, 2005 page 512 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics tcyc tCH tCL VOH CK 1/2VCC VOH VOL tCF VOL VOH 1/2VCC tCR Figure 22.2 System Clock Timing tEXcyc tEXH tEXL EXTAL VIH 1/2VCC VIH VIL tEXF VIL VIH 1/2VCC tEXR Figure 22.3 EXTAL Clock Input Timing CK VCC RES VCC min tosc2 Figure 22.4 Oscillation Settling Time Rev. 4.00 Dec 05, 2005 page 513 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics 22.3.3 Control Signal Timing Table 22.5 shows control signal timing. Table 22.5 Control Signal Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C 1 to +75C (Standard product)* , Ta = -40C to +85C (Wide temperature-range 1 product)* . Item RES rise time, fall time RES pulse width RES setup time MRES pulse width MRES setup time MD3 to MD0 setup time NMI rise time, fall time NMI setup time IRQ3 to IRQ0 setup time* (edge detection) 2 IRQ3 to IRQ0 setup time* (level detection) 2 Symbol tRESr, tRESf tRESW tRESS tMRESW tMRESS tMDS tNMIr, tNMIIf tNMIS tIRQES tIRQLS tNMIH tIRQEH tIRQOD Min 25 19 20 19 20 19 19 19 19 19 Max 200 200 100 Unit ns tcyc ns tcyc ns tcyc ns ns ns ns ns ns ns Figures Figure 22.5 Figure 22.6 Figure 22.7 NMI hold time IRQ3 to IRQ0 hold time IRQOUT output delay time Figure 22.8 Notes: 1. See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. 2. The RES, MRES, NMI and IRQ3 to IRQ0 signals are asynchronous inputs, but when the setup times shown here are observed, the signals are considered to have been changed at clock rise (RES, MRES) or fall (NMI and IRQ3 to IRQ0). If the setup times are not observed, the recognition of these signals may be delayed until the next clock rise or fall. Rev. 4.00 Dec 05, 2005 page 514 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics CK tRESS tRESW VIL tMDS tRESS VOH VIH RES VIH VIL MD3 to MD0 VIH VIL Figure 22.5 Reset Input Timing CK tMRESS MRES tMRESS VIH VIL tMRESW VIL Figure 22.6 Reset Input Timing Rev. 4.00 Dec 05, 2005 page 515 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics CK VOL VOL tNMIH NMI VIH VIL tIRQEH IRQ edge tNMIS VIH VIL tIRQES VIH VIL tIRQLS IRQ level VIL Figure 22.7 Interrupt Signal Input Timing CK VOH tIRQOD tIRQOD VOH IRQOUT VOL Figure 22.8 Interrupt Signal Output Timing Rev. 4.00 Dec 05, 2005 page 516 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics 22.3.4 Multi-Function Timer Pulse Unit (MTU)Timing Table 22.6 shows Multi-Function timer pulse unit timing. Table 22.6 Multi-Function Timer Pulse Unit Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (Standard product)*, Ta = -40C to +85C (Wide temperature-range product)*. Item Output compare output delay time Input capture input setup time Timer input setup time Timer clock pulse width (single edge specified) Timer clock pulse width (both edges specified) Timer clock pulse width (phase count mode) Note: * Symbol tTOCD tTICS tTCKS tTCKWH/L tTCKWH/L tTCKWH/L Min 19 20 1.5 2.5 2.5 Max 100 Unit ns ns ns tpcyc tpcyc tpcyc Figure 22.10 Figures Figure 22.9 See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. Rev. 4.00 Dec 05, 2005 page 517 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics CK tTOCD Output compare output tTICS Input capture input Figure 22.9 MTU Input/Output timing CK tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 22.10 MTU Clock Input Timing Rev. 4.00 Dec 05, 2005 page 518 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics 22.3.5 I/O Port Timing Table 22.7 shows I/O port timing. Table 22.7 I/O Port Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (Standard product)*, Ta = -40C to +85C (Wide temperature-range product)*. Item Port output data delay time Port input hold time Port input setup time Symbol tPWD tPRH tPRS Min 19 19 Max 100 Unit ns ns ns Figures Figure 22.11 [Operating precaution] The port input signals are asynchronous. They are, however, considered to have been changed at CK clock falling edge with two-state intervals shown in figure 22.11. If the setup times shown here are not observed, recognition may be delayed until the clock falling two states after that timing. Note: * See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. CK tPRS Port (read) tPWD Port (write) tPRH Figure 22.11 I/O Port Input/Output timing Rev. 4.00 Dec 05, 2005 page 519 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics 22.3.6 Watchdog Timer (WDT)Timing Table 22.8 shows watchdog timer timing. Table 22.8 Watchdog Timer Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (Standard product)*, Ta = -40C to +85C (Wide temperature-range product)*. Item WDTOVF delay time Note: * Symbol tWOVD Min Max 100 Unit ns Figures Figure 22.12 See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. CK VOH tWOVD VOH tWOVD WDTOVF Figure 22.12 WDT Timing Rev. 4.00 Dec 05, 2005 page 520 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics 22.3.7 Serial Communication Interface (SCI)Timing Table 22.9 shows serial communication interface timing. Table 22.9 Serial Communication Interface Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (Standard product)*, Ta = -40C to +85C (Wide temperature-range product)*. Item Input clock cycle Symbol tscyc tsckw tsckr tsckf tTxD tRxS tRxH Min 4 6 0.4 100 100 Max 0.6 1.5 1.5 100 Unit tpcyc tpcyc tscyc tpcyc tpcyc ns ns ns Figure 22.14 Figures Figure 22.13 Input clock cycle (clock sync) tscyc Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Received data setup time Received data hold time [Operating precaution] The inputs and outputs are asynchronous in asynchronous mode, but as shown in figure 22.14, the received data is considered to have been changed at CK clock rise (two-clock intervals). The transmit signals change with a reference of CK clock rise (two-clock intervals). Note: * See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. tsckw VIH SCK2, SCK3 VIH VIL VIL tsckr VIH VIH tsckf VIL tscyc Figure 22.13 SCI Input Timing Rev. 4.00 Dec 05, 2005 page 521 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics SCI input/output timing (clock synchronous mode) tscyc SCK2, SCK3 (input/output) tTxD TxD2, TxD3 (transmit data) tRxS RxD2, RxD3 (received data) tRxH SCI input/output timing (asynchronous mode) T1 VOH CK tTxD TxD2, TxD3 (transmit data) tRxS RxD2, RxD3 (received data) tRxH VOH Tn Figure 22.14 SCI Input/Output Timing Rev. 4.00 Dec 05, 2005 page 522 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics 22.3.8 Motor Management Timer (MMT) Timing Table 22.10 Motor Management Timer Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (Standard product)*, Ta = -40C to +85C (Wide temperature-range product)*. Item MMT output delay time PCIO input (when input is set) setup time PCIO input (when input is set) pulse width Note: * Symbol tMTOD tPCIS tPCIW Min 35 1.5 Max 100 Unit ns ns tpcyc Figures Figure 22.15 See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. CK tMTOD MMT output tPCIS PCIO input tPCIW Figure 22.15 MMT Input/Output Timing Rev. 4.00 Dec 05, 2005 page 523 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics 22.3.9 Port Output Enable (POE) Timing Table 22.11 Port Output Enable (POE) Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (Standard product)*, Ta = -40C to +85C (Wide temperature-range product)*. Item POE input setup time POE input pulse width Note: * Symbol tPOES tPOEW Min 100 1.5 Max Unit ns tpcyc Figures Figure 22.16 See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. CK tPOES POE input tPOEW Figure 22.16 POE Input/Output Timing Rev. 4.00 Dec 05, 2005 page 524 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics 22.3.10 A/D Converter Timing Table 22.12 shows A/D converter timing. Table 22.12 A/D Converter Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (Standard product)*, Ta = -40C to +85C (Wide temperature-range product)* Item External trigger input start delay time Note: * Symbol tTRGS Min 50 Typ Max Unit ns Figure Figure 22.17 See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. 3 to 5 states CK VOH ADTRG input tTRGS ADCR (ADST = 1 set) Figure 22.17 External Trigger Input Timing Rev. 4.00 Dec 05, 2005 page 525 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics 22.3.11 UBC Trigger Timing Table 22.13 shows UBC trigger timing. Table 22.13 UBC Trigger Timing Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C to +75C (Standard product)*, Ta = -40C to +85C (Wide temperature-range product)* Item UBCTRG delay time Note: * Symbol tUBCTGD Min Max 35 Unit ns Figures Figure 22.18 See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. CK VOH tUBCTGD UBCTRG Figure 22.18 UBC Trigger Timing Rev. 4.00 Dec 05, 2005 page 526 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics 22.4 A/D Converter Characteristics Table 22.14 shows A/D converter characteristics. Table 22.14 A/D Converter Characteristics Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C 3 to +75C (Standard product)* , Ta = -40C to +85C (Wide temperature-range 3 product)* Item Resolution A/D conversion time Analog input capacitance Permitted analog signal source impedance Non-linear error (reference value) Offset error (reference value) Full-scale error (reference value) Quantization error Absolute error Min 10 Typ 10 Max 10 Unit bit *1/5.4*2 s 6.7 20 1 2 3* /1* pF k LSB LSB LSB LSB 1 1 3.0* / 2 5.0* 3.0* / 2 5.0* 1 3.0* / 2 5.0* 1 0.5 4.0* / 2 6.0* LSB Notes: 1. Value when (CKS1, 0) = (11) and tpcyc = 50 ns 2. Value when (CKS1, 0) = (11) and tpcyc = 40 ns 3. See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. Rev. 4.00 Dec 05, 2005 page 527 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics 22.5 Flash Memory Characteristics Table 22.15 shows flash memory characteristics. Table 22.15 Flash Memory Characteristics Conditions: VCC = 4.0 V to 5.5 V, AVCC = 4.0 V to 5.5 V, VSS = PLLVSS = AVSS = 0 V, Ta = -20C 6 to +75C (Standard product)* , Ta = -40C to +85C (Wide temperature-range 6 product)* . Item Programming time*1, *2, *4 Erase time*1, *3, *5 Reprogramming count Symbol tP tE NWEC NWEC Min 100*7 -- Typ 10 100 Max 200 1200 Unit ms/ 128 bytes ms/block Times Times Standard product Wide temperaturerange product Remarks 8 10000* -- -- 100 Data retained time Programming Wait time after SWE bit setting*1 Wait time after PSU bit setting*1 Wait time after P bit setting*1 *4 tDRP tsswe tspsu tsp30 tsp200 tsp10 10*9 1 50 28 198 8 -- 1 50 30 200 10 -- 32 202 12 years s s s s s Programming time wait Programming time wait Additionalprogramming time wait Wait time after P bit clear*1 Wait time after PSU bit clear*1 Wait time after PV bit setting* Wait time after PV bit clear*1 Wait time after SWE bit clear*1 Maximum programming count*1, *4 1 tcp tcpsu tspv 5 5 4 2 2 100 5 5 4 2 2 100 1000 s s s s s s Times Wait time after H'FF dummy write*1 tspvr tcpv tcswe N Rev. 4.00 Dec 05, 2005 page 528 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics Item Erase Wait time after SWE bit setting* Wait time after E bit setting*1 *5 Wait time after E bit clear*1 Wait time after ESU bit clear* 1 1 Symbol tsswe tsesu tse tce tcesu tsev Min 1 100 10 10 10 20 2 4 100 12 Typ 1 100 10 10 10 20 2 4 100 Max 100 120 Unit s s ms s s s s s s Times Remarks Wait time after ESU bit setting*1 Erase time wait Wait time after EV bit setting*1 Wait time after EV bit clear*1 Wait time after SWE bit clear*1 Maximum erase count*1 *5 Notes: Wait time after H'FF dummy write*1 tsevr tcev tcswe N 1. Make each time setting in accordance with the program/program-verify algorithm or erase/eraseverify algorithm. 2. Programming time per 128 bytes (shows the total period for which the P-bit in the flash memory control register (FLMCR1) is set. It does not include the programming verification time.) 3. 1-Block erase time (shows the total period for which the E-bit in FLMCR1 is set. It does not include the erase verification time.) 4. To specify the maximum programming time value (tp (max)) in the 128-bytes programming algorithm, set the max. value (1000) for the maximum programming count (N). The wait time after P bit setting should be changed as follows according to the value of the programming counter (n). Programming counter (n) = 1 to 6: tsp30 = 30 s Programming counter (n) = 7 to 1000: tsp200 = 200 s [In additional programming] Programming counter (n) = 1 to 6: tsp10 = 10 s 5. For the maximum erase time (tE (max)), the following relationship applies between the wait time after E bit setting (tse) and the maximum erase count (N): tE(max) = Wait time after E bit setting (tse) x maximum erase count (N) To set the maximum erase time, the values of (tse) and (N) should be set so as to satisfy the above formula. Examples: When tse = 100 ms, N = 12 times When tse = 10 ms, N = 120 times 6. See page 2 for correspondence of the standard product, wide temperature-range product, and product model name. 7. All characteristics after rewriting are guaranteed up to this minimum rewriting times (therefore 1 to min. times). 8. Reference value at 25C (A rough rewriting target number to which a rewriting usually functions) 9. Data retention characteristics when rewriting is executed within the specification values including minimum values. Rev. 4.00 Dec 05, 2005 page 529 of 564 REJ09B0270-0400 Section 22 Electrical Characteristics Rev. 4.00 Dec 05, 2005 page 530 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Appendix A Internal I/O Register The column "Access Size" shows the number of bits. The column "Access States" shows the number of access states, in units of cycles, of the specified reference clock. B, W, and L in the column represent 8-bit, 16-bit, and 32-bit access, respectively. A.1 Register Addresses (Order of Address) Abbreviation Bits SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SMR_3 BRR_3 SCR_3 TDR_3 SSR_3 RDR_3 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Address H'FFFF8000 to H'FFFF81BF H'FFFF81C0 H'FFFF81C1 H'FFFF81C2 H'FFFF81C3 H'FFFF81C4 H'FFFF81C5 H'FFFF81C6 H'FFFF81C7 to H'FFFF81CF H'FFFF81D0 H'FFFF81D1 H'FFFF81D2 H'FFFF81D3 H'FFFF81D4 H'FFFF81D5 H'FFFF81D6 H'FFFF81D7 to H'FFFF81EF H'FFFF81F0 to H'FFFF81FF SCI 8, 16 (channel 3) 8 8, 16 8 8, 16 8 8 Module Access Size Access States In P cycles B: 2 W: 4 Register Name Serial mode register_2 Bit rate register_2 Serial control register_2 Transmit data register_2 Serial status register_2 Receive data register_2 Serial mode register_3 Bit rate register_3 Serial control register_3 Transmit data register_3 Serial status register_3 Receive data register_3 SCI 8, 16 (channel 2) 8 8, 16 8 8, 16 8 8 Serial direction control register_2 SDCR_2 Serial direction control register_3 SDCR_3 Rev. 4.00 Dec 05, 2005 page 531 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Access Size Access States Register Name Timer control register_3 Timer control register_4 Timer mode register_3 Timer mode register_4 Timer I/O control register H_3 Timer I/O control register L_3 Timer I/O control register H_4 Timer I/O control register L_4 Abbreviation Bits TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 TIORH_4 TIORL_4 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 Address H'FFFF8200 H'FFFF8201 H'FFFF8202 H'FFFF8203 H'FFFF8204 H'FFFF8205 H'FFFF8206 H'FFFF8207 H'FFFF8208 H'FFFF8209 H'FFFF820A H'FFFF820B H'FFFF820C H'FFFF820D H'FFFF820E H'FFFF820F H'FFFF8210 H'FFFF8212 H'FFFF8214 H'FFFF8216 H'FFFF8218 H'FFFF821A H'FFFF821C H'FFFF821E H'FFFF8220 H'FFFF8222 H'FFFF8224 H'FFFF8226 H'FFFF8228 H'FFFF822A H'FFFF822C H'FFFF822D H'FFFF822E to H'FFFF823F Module MTU (channels 3 and 4) 8, 16, 32 In P cycles B: 2 8 W: 2 8, 16 L: 4 8 8, 16, 32 8 8, 16 8 8, 16, 32 8 8, 16 8 Timer interrupt enable register_3 TIER_3 Timer interrupt enable register_4 TIER_4 Timer output master enable register Timer output control register Timer gate control register Timer counter_3 Timer counter_4 Timer period data register Timer dead time data register Timer general register A_3 Timer general register B_3 Timer general register A_4 Timer general register B_4 Timer sub-counter Timer period buffer register Timer general register C_3 Timer general register D_3 Timer general register C_4 Timer general register D_4 Timer status register_3 Timer status register_4 TOER TOCR TGCR TCNT_3 TCNT_4 TCDR TDDR TGRA_3 TGRB_3 TGRA_4 TGRB_4 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TSR_4 8 16, 32 16 16, 32 16 16, 32 16 16, 32 16 16, 32 16 16, 32 16 16, 32 16 8, 16 8 Rev. 4.00 Dec 05, 2005 page 532 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Access Size 8, 16 8 Access States In P cycles B: 2 W: 2 Register Name Timer start register Timer synchro register Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Abbreviation Bits TSTR TSYR TCR_0 TMDR_0 TIORH_0 TIORL_0 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 Address H'FFFF8240 H'FFFF8241 H'FFFF8242 to H'FFFF825F H'FFFF8260 H'FFFF8261 H'FFFF8262 H'FFFF8263 H'FFFF8264 H'FFFF8265 H'FFFF8266 H'FFFF8268 H'FFFF826A H'FFFF826C H'FFFF826E H'FFFF8270 to H'FFFF827F H'FFFF8280 H'FFFF8281 H'FFFF8282 H'FFFF8283 H'FFFF8284 H'FFFF8285 H'FFFF8286 H'FFFF8288 H'FFFF828A H'FFFF828C to H'FFFF829F Module MTU (common) MTU 8, 16, 32 In P cycles (channel 0) B: 2 8 W: 2 8, 16 L: 4 8 8, 16, 32 8 16 16, 32 16 16, 32 16 MTU 8, 16 (channel 1) 8 8 8, 16, 32 8 16 16, 32 16 Timer interrupt enable register_0 TIER_0 Timer status register_0 Timer counter_0 Timer general register A_0 Timer general register B_0 Timer general register C_0 Timer general register D_0 Timer control register_1 Timer mode register_1 Timer I/O control register_1 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 Timer interrupt enable register_1 TIER_1 Timer status register_1 Timer counter_1 Timer general register A_1 Timer general register B_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 Rev. 4.00 Dec 05, 2005 page 533 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Access Size Access States In P cycles B: 2 W: 2 L: 4 Register Name Timer control register_2 Timer mode register_2 Timer I/O control register_2 Abbreviation Bits TCR_2 TMDR_2 TIOR_2 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 Address H'FFFF82A0 H'FFFF82A1 H'FFFF82A2 H'FFFF82A3 H'FFFF82A4 H'FFFF82A5 H'FFFF82A6 H'FFFF82A8 H'FFFF82AA H'FFFF82AC to H'FFFF833F H'FFFF8340 to H'FFFF8347 H'FFFF8348 H'FFFF834A to H'FFFF834D H'FFFF834E H'FFFF8350 H'FFFF8352 H'FFFF8354 H'FFFF8356 H'FFFF8358 H'FFFF835A H'FFFF835C H'FFFF835E H'FFFF8360 H'FFFF8362 to H'FFFF8365 H'FFFF8366 H'FFFF8368 to H'FFFF837F H'FFFF8380 to H'FFFF8381 Module 8, 16 MTU (channel 2) 8 8 8, 16, 32 8 16 16, 32 16 INTC 8, 16 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 Timer interrupt enable register_2 TIER_2 Timer status register_2 Timer counter_2 Timer general register A_2 Timer general register B_2 Interrupt priority register A Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt control register 1 IRQ status register Interrupt priority register I Interrupt priority register J Interrupt priority register K Interrupt control register 2 TSR_2 TCNT_2 TGRA_2 TGRB_2 IPRA IPRD IPRE IPRF IPRG IPRH ICR1 ISR IPRI IPRJ IPRK ICR2 In cycles B: 2 W: 2 L: 4 Rev. 4.00 Dec 05, 2005 page 534 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Access Size 8, 16 Access States In cycles B: 2 W: 2 L: 4 Register Name Port A data register L Abbreviation Bits PADRL 16 Address H'FFFF8382 H'FFFF8384 to H'FFFF8385 H'FFFF8386 H'FFFF8388 to H'FFFF8389 H'FFFF838A H'FFFF838C H'FFFF838E H'FFFF8390 Module I/O Port A I/O register L Port A control register L3 Port A control register L1 Port A control register L2 Port B data register Port B I/O register Port B control register 1 Port B control register 2 Port E data register L Port F data register Port E I/O register L Port E I/O register H Port E control register L1 Port E control register L2 Port E control register H Port E data register H PAIORL PACRL3 PACRL1 PACRL2 PBDR PBIOR PBCR1 PBCR2 PEDRL PFDR PEIORL PEIORH PECRL1 PECRL2 PECRH PEDRH 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 PFC PFC 8, 16 8, 16 8, 16, 32 8, 16 I/O 8, 16 8, 16, 32 8, 16, 32 8, 16 8, 16, 32 8, 16 H'FFFF8392 to H'FFFF8393 H'FFFF8394 H'FFFF8396 to H'FFFF8397 H'FFFF8398 H'FFFF839A H'FFFF839C to H'FFFF83A1 H'FFFF83A2 H'FFFF83A4 to H'FFFF83A5 H'FFFF83A6 H'FFFF83A8 to H'FFFF83AB H'FFFF83AC H'FFFF83AE H'FFFF83B0 H'FFFF83B2 H'FFFF83B4 H'FFFF83B6 H'FFFF83B8 H'FFFF83BA H'FFFF83BC H'FFFF83BE I/O PFC I/O PFC PFC 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16, 32 8, 16 Rev. 4.00 Dec 05, 2005 page 535 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Access Size Access States Register Name Input control/status register 1 Output control/status register Input control/status register 2 Port G data register Abbreviation Bits ICSR1 OCSR ICSR2 PGDR 16 16 16 8 Address H'FFFF83C0 H'FFFF83C2 H'FFFF83C4 Module MTU MMT 8, 16, 32 In P cycles B: 2 8, 16 W: 2 8, 16 L: 4 8 In cycles B: 2 W: 2 L: 4 H'FFFF83C6 to H'FFFF83CC H'FFFF83CD I/O Compare match timer start register Compare match timer control/status register_0 Compare match timer counter_0 Compare match timer constant register_0 Compare match timer control/status register_1 Compare match timer counter_1 Compare match timer constant register_1 A/D data register 8 A/D data register 9 A/D data register 10 A/D data register 11 A/D data register 12 A/D data register 13 A/D data register 14 A/D data register 15 CMSTR CMCSR_0 CMCNT_0 CMCOR_0 CMCSR_1 CMCNT_1 CMCOR_1 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 H'FFFF83CE to H'FFFF83CF H'FFFF83D0 H'FFFF83D2 H'FFFF83D4 H'FFFF83D6 H'FFFF83D8 H'FFFF83DA H'FFFF83DC H'FFFF83DE H'FFFF83E0 to H'FFFF842F H'FFFF8430 H'FFFF8432 H'FFFF8434 H'FFFF8436 H'FFFF8438 H'FFFF843A H'FFFF843C H'FFFF843E CMT 8, 16, 32 In P cycles B: 2 W: 2 8, 16 L: 4 8, 16, 32 8, 16 8, 16, 32 8, 16 8, 16 In P cycles B: 3 W: 6 8, 16 A/D (channel 0) 8, 16 8, 16 8, 16 A/D 8, 16 (channel 1) 8, 16 8, 16 8, 16 Rev. 4.00 Dec 05, 2005 page 536 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Access Size Access States In P cycles B: 3 W: 6 Register Name A/D data register 16 A/D data register 17 A/D data register 18 A/D data register 19 A/D control/status register_0 A/D control/status register_1 A/D control/status register_2 A/D control register_0 A/D control register_1 A/D control register_2 Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 User break address register H User break address register L Abbreviation Bits ADDR16 ADDR17 ADDR18 ADDR19 ADCSR_0 ADCSR_1 ADCSR_2 ADCR_0 ADCR_1 ADCR_2 FLMCR1 FLMCR2 EBR1 EBR2 UBARH UBARL 16 16 16 16 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 Address H'FFFF8440 H'FFFF8442 H'FFFF8444 H'FFFF8446 Module 8, 16 A/D (channel 2) 8, 16 8, 16 8, 16 8, 16 8 8 8, 16 8 8 FLASH (F-ZTAT only) 8, 16 8 8, 16 8 UBC H'FFFF8448 to H'FFFF847F H'FFFF8480 H'FFFF8481 H'FFFF8482 H'FFFF8483 to H'FFFF8487 H'FFFF8488 H'FFFF8489 H'FFFF848A H'FFFF848B to H'FFFF857F H'FFFF8580 H'FFFF8581 H'FFFF8582 H'FFFF8583 H'FFFF8584 to H'FFFF85FF H'FFFF8600 H'FFFF8602 H'FFFF8604 H'FFFF8606 H'FFFF8608 H'FFFF860A H'FFFF860C to H'FFFF860F A/D In cycles B: 3 W: 6 8, 16 User break address mask register UBAMRH H User break address mask register UBAMRL L User break bus cycle register User break control register UBBR UBCR 8, 16, 32 In cycles B: 3 W: 3 8, 16, 32 L: 6 8, 16 8, 16, 32 8, 16 Rev. 4.00 Dec 05, 2005 page 537 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Access Size 8*2/16*1 16 8 16 8 Power8 down state 8 8, 16, 32 8, 16 BSC 8, 16, 32 In cycles B: 3 W: 3 L: 6 8, 16 In cycles B: 3 W: 3 In cycles B: 3 In P cycles B: 3 W: 3 L: 6 Access States In cycles B: 3 W: 3 Register Name Timer control/status register Timer counter Timer counter Reset control/status register Reset control/status register Standby control register System control register Abbreviation Bits TCSR TCNT* 1 Address H'FFFF8610 H'FFFF8610 H'FFFF8611 H'FFFF8612 H'FFFF8613 H'FFFF8614 H'FFFF8615 to H'FFFF8617 H'FFFF8618 H'FFFF8619 to H'FFFF861B H'FFFF861C H'FFFF861E H'FFFF8620 H'FFFF8622 to H'FFFF8626 H'FFFF8628 Module WDT *1: Write cycle *2: Read cycle 8 8 8 8 8 8 8 16 16 16 TCNT*2 RSTCSR*1 RSTCSR*2 SBYCR SYSCR Module standby control register 1 MSTCR1 Module standby control register 2 MSTCR2 Bus control register 1 BCR1 RAM emulation register RAMER 16 FLASH DTC enable register A DTC enable register B DTC enable register C DTC enable register D DTEA DTEB DTEC DTED DTC control/status register DTC information base register DTCSR DTBR 8 8 8 8 16 16 H'FFFF862A to H'FFFF864F H'FFFF8650 to H'FFFF86FF H'FFFF8700 H'FFFF8701 H'FFFF8702 H'FFFF8703 H'FFFF8704 to H'FFFF8705 H'FFFF8706 H'FFFF8708 H'FFFF870A to H'FFFF870F DTC 8, 16, 32 In cycles B: 3 8 W: 3 8, 16 L: 6 8 8, 16 8, 16 Rev. 4.00 Dec 05, 2005 page 538 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Access Size 8, 16 8 A/D 8 MMT 8 8 8 16 16, 32 16 16 16, 32 16 16, 32 16 16, 32 16 16 16, 32 16 16, 32 In P cycles W: 2 L: 4 Access States In cycles B: 3 W: 3 L: 6 In P cycles B: 3 Register Name DTC enable register E DTC enable register F Abbreviation Bits DTEE DTEF 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Address H'FFFF8710 H'FFFF8711 H'FFFF8712 to H'FFFF87F3 H'FFFF87F4 H'FFFF87F5 to H'FFFF89FF H'FFFF8A00 H'FFFF8A01 H'FFFF8A02 H'FFFF8A03 H'FFFF8A04 H'FFFF8A05 H'FFFF8A06 H'FFFF8A08 H'FFFF8A0A H'FFFF8A0C H'FFFF8A0E to H'FFFF8A0F H'FFFF8A10 H'FFFF8A12 H'FFFF8A14 H'FFFF8A16 H'FFFF8A18 H'FFFF8A1A H'FFFF8A1C H'FFFF8A1E to H'FFFF8A1F H'FFFF8A20 H'FFFF8A22 H'FFFF8A24 Module DTC AD trigger select register ADTSR Timer mode register MMT_TMDR Timer control register TCNR In P cycles B: 2 W: 2 L: 4 Timer status register MMT_TSR Timer counter Timer period data register Timer period buffer register Timer dead time data register MMT_TCNT TPDR TPBR MMT_TDDR Timer buffer register U_B Timer general register UU Timer general register U Timer general register UD Timer dead time counter 0 Timer dead time counter 1 Timer buffer register U_F TBRU_B TGRUU TGRU TGRUD TDCNT0 TDCNT1 TBRU_F Timer buffer register V_B Timer general register VU Timer general register V TBRV_B TGRVU TGRV Rev. 4.00 Dec 05, 2005 page 539 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Access Size 16 16, 32 16 16 16, 32 16 16, 32 16 16, 32 16 16 Access States In P cycles W: 2 L: 4 Register Name Timer general register VD Timer dead time counter 2 Timer dead time counter 3 Timer buffer register V_F Abbreviation Bits TGRVD TDCNT2 TDCNT3 TBRV_F 16 16 16 16 16 16 16 16 16 16 16 Address H'FFFF8A26 H'FFFF8A28 H'FFFF8A2A H'FFFF8A2C H'FFFF8A2E to H'FFFF8A2F H'FFFF8A30 H'FFFF8A32 H'FFFF8A34 H'FFFF8A36 H'FFFF8A38 H'FFFF8A3A H'FFFF8A3C H'FFFF8A3E to H'FFFFB4F3 Module MMT Timer buffer register W_B Timer general register WU Timer general register W Timer general register WD Timer dead time counter 4 Timer dead time counter 5 Timer buffer register W_F TBRW_B TGRWU TGRW TGRWD TDCNT4 TDCNT5 TBRW_F Rev. 4.00 Dec 05, 2005 page 540 of 564 REJ09B0270-0400 Appendix A Internal I/O Register A.2 Register Bits Internal peripheral module register addresses and bit names are shown in the following table. 16-bit and 32-bit registers are shown in two and four rows of 8 bits, respectively. Register Abbreviation SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SDCR_2 SMR_3 BRR_3 SCR_3 TDR_3 SSR_3 RDR_3 SDCR_3 TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 TIORH_4 TIORL_4 TIER_3 TIER_4 TOER TOCR TGCR TCNT_3 CCLR2 CCLR2 IOB3 IOD3 IOB3 IOD3 TTGE TTGE CCLR1 CCLR1 IOB2 IOD2 IOB2 IOD2 PSYE BDC CCLR0 CCLR0 BFB BFB IOB1 IOD1 IOB1 IOD1 OE4D N CKEG1 CKEG1 BFA BFA IOB0 IOD0 IOB0 IOD0 TCIEV TCIEV OE4C P DIR CKEG0 CKEG0 MD3 MD3 IOA3 IOC3 IOA3 IOC3 TGIED TGIED OE3D FB TPSC2 TPSC2 MD2 MD2 IOA2 IOC2 IOA2 IOC2 TGIEC TGIEC OE4B WF TPSC1 TPSC1 MD1 MD1 IOA1 IOC1 IOA1 IOC1 TGIEB TGIEB OE4A OLSN VF TPSC0 TPSC0 MD0 MD0 IOA0 IOC0 IOA0 IOC0 TGIEA TGIEA OE3B OLSP UF MTU (channels 3 and 4) TDRE RDRF ORER FER PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 C/A CHR PE O/E DIR STOP MP CKS1 CKS0 SCI (channel 3) TDRE RDRF ORER FER PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 Bit 7 C/A Bit 6 CHR Bit 5 PE Bit 4 O/E Bit 3 STOP Bit 2 MP Bit 1 CKS1 Bit 0 CKS0 Module SCI (channel 2) Rev. 4.00 Dec 05, 2005 page 541 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Register Abbreviation TCNT_4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MTU (channels 3 and 4) TCDR TDDR TGRA_3 TGRB_3 TGRA_4 TGRB_4 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TSR_4 TSTR TSYR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TCFD TCFD CST4 SYNC4 CCLR2 IOB3 IOD3 TTGE CST3 SYNC3 CCLR1 IOB2 IOD2 CCLR0 BFB IOB1 IOD1 TCFV TCFV CKEG1 BFA IOB0 IOD0 TCIEV TGFD TGFD CKEG0 MD3 IOA3 IOC3 TGIED TGFC TGFC CST2 SYNC2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFB TGFB CST1 SYNC1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFA TGFA CST0 SYNC0 TPSC0 MD0 IOA0 IOC0 TGIEA MTU (channel 0) Rev. 4.00 Dec 05, 2005 page 542 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Register Abbreviation TSR_0 TCNT_0 Bit 7 Bit 6 Bit 5 Bit 4 TCFV Bit 3 TGFD Bit 2 TGFC Bit 1 TGFB Bit 0 TGFA Module MTU (channel 0) TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 IOB3 TTGE TCFD CCLR1 IOB2 CCLR0 IOB1 TCIEU TCFU CKEG1 IOB0 TCIEV TCFV CKEG0 MD3 IOA3 TPSC2 MD2 IOA2 TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA MTU (channel 1) TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 IOB3 TTGE TCFD CCLR1 IOB2 CCLR0 IOB1 TCIEU TCFU CKEG1 IOB0 TCIEV TCFV CKEG0 MD3 IOA3 TPSC2 MD2 IOA2 TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA MTU (channel 2) TGRA_2 TGRB_2 Rev. 4.00 Dec 05, 2005 page 543 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Register Abbreviation IPRA Bit 7 IRQ0 IRQ2 Bit 6 IRQ0 IRQ2 MTU0 MTU1 MTU2 MTU3 MTU4 A/D0,1 CMT0 WDT IRQ1S IRQ1F SCI2 A/D2 I/O(MMT) IRQ0ES0 PA14DR PA6DR PA14IOR PA6IOR Bit 5 IRQ0 IRQ2 MTU0 MTU1 MTU2 MTU3 MTU4 A/D0,1 CMT0 WDT IRQ2S IRQ2F SCI2 A/D2 I/O(MMT) IRQ1ES1 PA13DR PA5DR PA13IOR PA5IOR Bit 4 IRQ0 IRQ2 MTU0 MTU1 MTU2 MTU3 MTU4 A/D0,1 CMT0 WDT IRQ3S IRQ3F SCI2 A/D2 I/O(MMT) IRQ1ES0 PA12DR PA4DR PA12IOR PA4IOR Bit 3 IRQ1 IRQ3 MTU0 MTU1 MTU2 MTU3 MTU4 DTC CMT1 I/O(MTU) SCI3 MMT IRQ2ES1 PA11DR PA3DR PA11IOR PA3IOR Bit 2 IRQ1 IRQ3 MTU0 MTU1 MTU2 MTU3 MTU4 DTC CMT1 I/O(MTU) SCI3 MMT IRQ2ES0 PA10DR PA2DR PA10IOR PA2IOR Bit 1 IRQ1 IRQ3 MTU0 MTU1 MTU2 MTU3 MTU4 DTC CMT1 I/O(MTU) SCI3 MMT IRQ3ES1 PA9DR PA1DR PA9IOR PA1IOR Bit 0 IRQ1 IRQ3 MTU0 MTU1 MTU2 MTU3 MTU4 DTC CMT1 I/O(MTU) NMIE SCI3 MMT IRQ3ES0 PA8DR PA0DR PA8IOR PA0IOR PA8MD2 PA0MD2 Module INTC IPRD MTU0 MTU1 IPRE MTU2 MTU3 IPRF MTU4 IPRG A/D0,1 CMT0 IPRH WDT ICR1 NMIL IRQ0S ISR IRQ0F IPRI SCI2 IPRJ A/D2 IPRK I/O(MMT) ICR2 IRQ0ES1 PADRL PA15DR PA7DR Port A PAIORL PA15IOR PA7IOR PACRL3 PA15MD2 PA14MD2 PA13MD2 PA12MD2 PA11MD2 PA10MD2 PA9MD2 PA7MD2 PA6MD2 PA5MD2 PA4MD2 PA3MD2 PA2MD2 PA1MD2 PACRL1 PA15MD1 PA15MD0 PA14MD1 PA14MD0 PA13MD1 PA13MD0 PA12MD1 PA12MD0 PA11MD1 PA11MD0 PA10MD1 PA10MD0 PA9MD1 PA9MD0 PA5MD0 PA1MD0 PA8MD1 PA4MD1 PA0MD1 PA8MD0 PA4MD0 PA0MD0 PACRL2 PA7MD1 PA3MD1 PA7MD0 PA3MD0 PA6MD1 PA2MD1 PA6MD0 PA2MD0 PA5MD1 PA1MD1 Rev. 4.00 Dec 05, 2005 page 544 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Register Abbreviation PBDR Bit 7 Bit 6 PB3MD0 PE14DR PE6DR PF14DR PF6DR Bit 5 PB5DR PB5IOR PB5MD2 PB2MD1 PE13DR PE5DR PF13DR PF5DR Bit 4 PB4DR PB4 IOR PB4MD2 PB2MD0 PE12DR PE4DR PF12DR PF4DR Bit 3 PB3DR PB3 IOR PB3MD2 PB5MD1 PE11DR PE3DR PF11DR PF3DR Bit 2 PB2DR PB2 IOR PB2MD2 PB5MD0 PE10DR PE2DR PF10DR PF2DR Bit 1 PB4MD1 PE9DR PE1DR PF9DR PF1DR Bit 0 PB4MD0 PE8DR PE0DR PF8DR PF0DR PE8 IOR PE0 IOR PE16IOR Module Port B PBIOR PBCR1 PBCR2 PB3MD1 PEDRL PE15DR PE7DR Port E PFDR PF15DR PF7DR Port F PEIORL PE15IOR PE7 IOR PE14 IOR PE13 IOR PE12 IOR PE11 IOR PE10 IOR PE9 IOR PE6 IOR PE5 IOR PE21IOR PE4 IOR PE20IOR PE3 IOR PE19IOR PE2 IOR PE18IOR PE1 IOR PE17IOR Port E PEIORH PECRL1 PE15MD1 PE15MD0 PE14MD1 PE14MD0 PE13MD1 PE13MD0 PE12MD1 PE12MD0 PE11MD1 PE11MD0 PE10MD1 PE10MD0 PE9MD1 PE9MD0 PE5MD0 PE1MD0 PE8MD1 PE4MD1 PE0MD1 PE8MD0 PE4MD0 PE0MD0 PECRL2 PE7MD1 PE3MD1 PE7MD0 PE3MD0 PE6MD1 PE2MD1 PE6MD0 PE2MD0 PE5MD1 PE1MD1 PECRH PE21MD1 PE21MD0 PE20MD1 PE20MD0 PE19MD1 PE19MD0 PE18MD1 PE18MD0 PE17MD1 PE17MD0 PE16MD1 PE16MD0 PEDRH ICSR1 POE3F POE3M1 OCSR OSF ICSR2 PGDR POE2F POE3M0 POE6F PE21DR POE1F POE2M1 POE5F POE6M1 PE20DR POE0F POE2M0 POE4F POE6M0 PE19DR POE1M1 POE5M1 PG3DR PE18DR POE1M0 POE5M0 PG2DR PE17DR POE0M1 OCE POE4M1 PG1DR PE16DR PIE POE0M0 OIE PIE POE4M0 PG0DR Port G MMT MTU Rev. 4.00 Dec 05, 2005 page 545 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Register Abbreviation CMSTR Bit 7 Bit 6 CMIE Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 STR1 CKS1 Bit 0 STR0 CKS0 Module CMT CMCSR_0 CMF CMCNT_0 CMCOR_0 CMCSR_1 CMF CMIE CKS1 CKS0 CMCNT_1 CMCOR_1 ADDR8 AD9 AD1 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 AD7 AD7 AD7 AD7 AD7 AD7 AD7 AD7 AD7 AD7 AD6 AD6 AD6 AD6 AD6 AD6 AD6 AD6 AD6 AD6 AD5 AD5 AD5 AD5 AD5 AD5 AD5 AD5 AD5 AD5 AD4 AD4 AD4 AD4 AD4 AD4 AD4 AD4 AD4 AD4 AD3 AD3 AD3 AD3 AD3 AD3 AD3 AD3 AD3 AD3 AD2 AD2 AD2 AD2 AD2 AD2 AD2 AD2 AD2 AD2 A/D ADDR9 AD9 AD1 ADDR10 AD9 AD1 ADDR11 AD9 AD1 ADDR12 AD9 AD1 ADDR13 AD9 AD1 ADDR14 AD9 AD1 ADDR15 AD9 AD1 ADDR16 AD9 AD1 ADDR17 AD9 AD1 Rev. 4.00 Dec 05, 2005 page 546 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Register Abbreviation ADDR18 Bit 7 AD9 AD1 Bit 6 AD8 AD0 AD8 AD0 ADIE ADIE ADIE CKS1 CKS1 CKS1 SWE EB6 UBA30 UBA22 UBA14 UBA6 UBM30 UBM22 UBM14 UBM6 CP0 WT/IT Bit 5 AD7 AD7 ADM1 ADM1 ADM1 CKS0 CKS0 CKS0 ESU EB5 UBA29 UBA21 UBA13 UBA5 UBM29 UBM21 UBM13 UBM5 ID1 TME Bit 4 AD6 AD6 ADM0 ADM0 ADM0 ADST ADST ADST PSU EB4 UBA28 UBA20 UBA12 UBA4 UBM28 UBM20 UBM12 UBM4 ID0 Bit 3 AD5 AD5 ADCS ADCS ADCS EV EB3 EB11 UBA27 UBA19 UBA11 UBA3 UBM27 UBM19 UBM11 UBM3 RW1 Bit 2 AD4 AD4 CH2 CH2 CH2 PV EB2 EB10 UBA26 UBA18 UBA10 UBA2 UBM26 UBM18 UBM10 UBM2 RW0 CKS1 CKS2 Bit 1 AD3 AD3 CH1 CH1 CH1 E EB1 EB9 UBA25 UBA17 UBA9 UBA1 UBM25 UBM17 UBM9 UBM1 SZ1 CKS0 CKS1 Bit 0 AD2 AD2 CH0 CH0 CH0 P EB0 EB8 UBA24 UBA16 UBA8 UBA0 UBM24 UBM16 UBM8 UBM0 SZ0 UBID CKS0 Module A/D ADDR19 AD9 AD1 ADCSR_0 ADCSR_1 ADCSR_2 ADCR_0 ADCR_1 ADCR_2 FLMCR1 FLMCR2 EBR1 EBR2 UBARH ADF ADF ADF TRGE TRGE TRGE FWE FLER EB7 UBA31 UBA23 FLASH (F-ZTAT only) UBC UBARL UBA15 UBA7 UBAMRH UBM31 UBM23 UBAMRL UBM15 UBM7 UBBR CP1 UBCR TCSR TCNT RSTCSR OVF WDT WOVF RSTE RSTS Rev. 4.00 Dec 05, 2005 page 547 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Register Abbreviation SBYCR SYSCR MSTCR1 Bit 7 SSBY Bit 6 HIZ MSTP14 MSTP6 Bit 5 MSTP13 MSTP5 Bit 4 MSTP12 MSTP4 Bit 3 MSTP27 MSTP19 RAMS DTEA3 DTEB3 DTEC3 DTED3 DTVEC3 Bit 2 MSTP26 MSTP18 RAM2 DTEA2 DTEB2 DTEC2 DTED2 NMIF DTVEC2 Bit 1 MSTP25 RAM1 DTEA1 DTEB1 DTEC1 DTED1 AE DTVEC1 Bit 0 IRQEL RAME MSTP24 MSTP0 RAM0 DTEA0 DTEB0 DTEC0 DTED0 SWDTE DTVEC0 Module Power-down state MSTCR2 BCR1 BSC MMTRWE MTURWE DTEA6 DTEB6 DTEC6 DTED6 DTVEC6 DTEA5 DTEB5 DTEC5 DTED5 DTVEC5 DTEA4 DTEB4 DTEC4 DTED4 DTVEC4 RAMER FLASH DTEA DTEB DTEC DTED DTCSR DTEA7 DTEB7 DTEC7 DTED7 DTVEC7 DTC DTBR DTEE DTEF ADTSR MMT_TMDR TCNR MMT_TSR MMT_TCNT DTEF7 TTGE TCFD DTEF6 CKS2 CST DTEE5 DTEF5 TRG2S1 CKS1 RPRO DTEE4 DTEF4 TRG2S0 CKS0 DTEE3 TRG1S1 OLSN DTEE2 DTEF2 TRG1S0 OLSP DTEE1 TRG0S1 MD1 TGIEN TGFN DTEE0 TRG0S0 MD0 TGIEM TGFM A/D MMT TPDR TPBR MMT_TDDR Rev. 4.00 Dec 05, 2005 page 548 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Register Abbreviation TBRU_B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MMT TGRUU TGRU TGRUD TDCNT0 TDCNT1 TBRU_F TBRV_B TGRVU TGRV TGRVD TDCNT2 TDCNT3 TBRV_F TBRW_B TGRWU TGRW TGRWD Rev. 4.00 Dec 05, 2005 page 549 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Register Abbreviation TDCNT4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module MMT TDCNT5 TBRW_F Rev. 4.00 Dec 05, 2005 page 550 of 564 REJ09B0270-0400 Appendix A Internal I/O Register A.3 Register States in Each Operating Mode Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held MTU (channels 3 and 4) SCI (channel 3) Module SCI (channel 2) Register Abbreviation SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SDCR_2 SMR_3 BRR_3 SCR_3 TDR_3 SSR_3 RDR_3 SDCR_3 TCR_3 TCR_4 TMDR_3 TMDR_4 TIORH_3 TIORL_3 TIORH_4 TIORL_4 TIER_3 TIER_4 TOER TOCR TGCR TCNT_3 TCNT_4 TCDR TDDR Rev. 4.00 Dec 05, 2005 page 551 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Register Abbreviation TGRA_3 TGRB_3 TGRA_4 TGRB_4 TCNTS TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4 TSR_3 TSR_4 TSTR TSYR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module MTU (channels 3 and 4) MTU (channel 0) Rev. 4.00 Dec 05, 2005 page 552 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Register Abbreviation TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 IPRA IPRD IPRE IPRF IPRG IPRH ICR1 ISR IPRI IPRJ IPRK ICR2 PADRL PAIORL PACRL3 PACRL1 PACRL2 PBDR PBIOR PBCR1 PBCR2 PEDRL PFDR Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Manual Reset Held Held Held Held Held Held Held Held Held Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Held Held Held Held Held Held Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module MTU (channel 2) INTC Port A Port B Port E Port F Rev. 4.00 Dec 05, 2005 page 553 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Register Abbreviation PEIORL PEIORH PECRL1 PECRL2 PECRH PEDRH ICSR1 OCSR ICSR2 PGDR CMSTR CMCSR_0 CMCNT_0 CMCOR_0 CMCSR_1 CMCNT_1 CMCOR_1 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADCSR_0 ADCSR_1 ADCSR_2 Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Software Standby Held Held Held Held Held Held Held Held Held Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Standby Held Held Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module Port E MTU MMT Port G CMT A/D Rev. 4.00 Dec 05, 2005 page 554 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Register Abbreviation ADCR_0 ADCR_1 ADCR_2 FLMCR1 FLMCR2 EBR1 EBR2 UBARH UBARL UBAMRH UBAMRL UBBR UBCR TCSR TCNT RSTCSR SBYCR SYSCR MSTCR1 MSTCR2 BCR1 RAMER DTEA DTEB DTEC DTED DTCSR DTBR DTEE DTEF ADTSR Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized/ Held*2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Initialized Initialized Initialized Manual Reset Held Held Held Initialized Initialized Initialized Initialized Held Held Held Held Held Held Initialized Initialized Held Initialized Held Held Held Held Held Held Held Held Held Held Held Held Held Held Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Held Initialized/ Held*1 Initialized Initialized Held Held Held Held Held Held Initialized Initialized Initialized Initialized Initialized Held Initialized Initialized Held Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Initialized Initialized Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module A/D FLASH UBC WDT Power-down state BSC FLASH DTC A/D Rev. 4.00 Dec 05, 2005 page 555 of 564 REJ09B0270-0400 Appendix A Internal I/O Register Register Abbreviation MMT_TMDR TCNR MMT_TSR MMT_TCNT TPDR TPBR MMT_TDDR TBRU_B TGRUU TGRU TGRUD TDCNT0 TDCNT1 TBRU_F TBRV_B TGRVU TGRV TGRVD TDCNT2 TDCNT3 TBRV_F TBRW_B TGRWU TGRW TGRWD TDCNT4 TDCNT5 TBRW_F Power-On Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Software Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module MMT Notes: 1. The bits 7 to 5 (OVF, WT/IT, and TME) in TCSR are initialized and the bits 2 to 0 (CKS2 to CKS0) are retained. 2. RSTCSR is retained in spite of power-on reset by WDT overflow. Rev. 4.00 Dec 05, 2005 page 556 of 564 REJ09B0270-0400 Appendix B Pin States Appendix B Pin States The initial values differ in each MCU operating mode. For details, refer to section 16, Pin Function Controller (PFC). Table B.1 Pin States Pin Function Reset State Type Pin Name Power-On Single-Chip Clock XTAL EXTAL PLLCAP System Control RES MRES WDTOVF Operation Mode Control Interrupt MD0 to MD3 FWP NMI IRQ0 to IRQ3 IRQOUT MTU TCLKA to TCLKD TIOC0A to TIOC0D TIOC1A, TIOC1B TIOC2A, TIOC2B TIOC3A, TIOC3C TIOC3B, TIOC3D TIOC4A to TIOC4D MMT PCIO PUOA, PUOB PVOA, PVOB PWOA, PWOB Z Z I/O O 1 K* 2 Z* Pin State Power-Down State Software Standby L I I I Z* O I I I 4 Z* 1 K* 2 Manual O I I I I O I I I I O I I/O Sleep O I I I I O I I I I O I I/O O I I I Z 3 O* I I I Z Z Z Z Z 1 K* Z I/O Z* 2 I/O I/O O Rev. 4.00 Dec 05, 2005 page 557 of 564 REJ09B0270-0400 Appendix B Pin States Pin Function Reset State Type Pin Name POE0 to POE6 SCK2, SCK3 RXD2, RXD3 TXD2, TXD3 A/D converter AN8 to AN19 ADTRG I/O port PA0 to PA15 PB0 to PB5 PE0 to PE8, PE10 PE9, PE11 to PE21 PF0 to PF15 PG0 to PG3 UBC UBCTRG Z Z Z Z I/O I I O 2 Z* Pin State Power-Down State Software Standby Z Z Z 1 O* Z Z 1 K* Sleep I I/O I O I I I/O Power-On Single-Chip Manual I I/O I O I I I/O Port control SCI Z Z Z Z Z Z Z I/O I I O Z Z 1 O* Legend: I: Input O: Output H: High-level output L: Low-level output Z: High impedance K: Input pins become high-impedance, and output pins retain their state. Notes: 1. When the HIZ bit in SBYCR is set to 1, the output pins enter their high-impedance state. 2. Those pins multiplexed with large-current pins unconditionally enter their highimpedance state. 3. This pin operates as an input pin during a power-on reset. This pin should be pulled up to avoid mulfunction. 4. This pin operates as an input pin when the IRQEL bit in SBYCR is cleared to 0. Rev. 4.00 Dec 05, 2005 page 558 of 564 REJ09B0270-0400 Appendix C Product Code Lineup Appendix C Product Code Lineup Product Type SH7046 Flash memory version Mask ROM version Standard product Standard product Product Code HD64F7046 HD6437048 HD6437148 Package (Previous Code) PRQP0080JD-A (FP-80Q) PRQP0080JD-A (FP-80Q) Rev. 4.00 Dec 05, 2005 page 559 of 564 REJ09B0270-0400 Appendix D Package Dimensions Appendix D Package Dimensions JEITA Package Code P-QFP80-14x14-0.65 RENESAS Code PRQP0080JD-A Previous Code FP-80Q/FP-80QV MASS[Typ.] 1.2g HD *1 D 60 41 61 40 bp b1 c1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. *2 HE E c Terminal cross section 80 21 ZE Reference Dimension in Millimeters Symbol 1 ZD 20 A2 A1 L L1 Detail F e *3 y bp x M Figure D.1 PRQP0080JD-A Rev. 4.00 Dec 05, 2005 page 560 of 564 REJ09B0270-0400 c F D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Nom Max 14 14 2.70 17.0 17.2 17.4 17.0 17.2 17.4 3.05 0.00 0.10 0.25 0.24 0.32 0.40 0.30 0.12 0.17 0.22 0.15 0 8 0.65 0.12 0.10 0.83 0.83 0.6 0.8 1.0 1.6 Min A Index Index A/D converter ......................................... 369 A/D conversion time........................... 379 Continuous scan mode ........................ 378 Single mode ........................................ 377 Single-cycle scan ................................ 378 Absolute maximum ratings..................... 507 Address map ............................................. 42 Addressing modes..................................... 17 Bus state controller ................................. 129 Clock mode............................................... 40 Clock pulse generator ............................... 47 Crystal oscillator ................................... 47 External clock ....................................... 48 Compare match timer ............................. 387 Control registers........................................ 11 Global Base Register (GBR)................. 11 Status Register (SR).............................. 11 Vector Base Register (VBR)................. 11 Data Formats............................................. 13 Byte....................................................... 13 Longword.............................................. 13 Word ..................................................... 13 Data transfer controller ........................... 105 Block Transfer Mode .......................... 120 Chain Transfer .................................... 122 DTC vector table................................. 115 DTC with interrupt activation............. 125 DTC with software activation ............. 125 Normal Mode...................................... 119 Repeat Mode....................................... 119 Delayed branch instructions...................... 15 Exception processing ................................ 53 Exception processing vector table Address error exception processing ...... 60 General illegal instruction exception processing .............................................63 Illegal slot exception processing ...........63 Interrupt exception processing ..............61 Manual reset..........................................58 Power-on reset.......................................57 Trap instruction exception processing...62 Exception processing Vector table............55 Flash memory..........................................459 Boot mode...........................................471 Error protection ...................................481 Flash Memory Emulation in RAM......474 Hardware protection............................480 Programmer mode...............................482 Software protection .............................480 User program mode.............................473 General registers .........................................9 I/O Ports ..................................................449 Interrupt controller ....................................67 Interrupt response time..........................85 IRQ interrupts .......................................77 NMI interrupt ........................................77 User break interrupt ..............................78 Vector numbers .....................................79 Vector table ...........................................79 Mask ROM..............................................489 Motor Management Timer ......................397 High-impedance state..........................426 Multi-function timer pulse unit ...............133 Buffer operation ..................................185 Cascaded operation .............................189 Compare match ...................................180 Free-running counters .........................179 High-impedance state..........................293 Rev. 4.00 Dec 05, 2005 page 561 of 564 REJ09B0270-0400 Index Input capture ....................................... 182 Phase counting mode .......................... 196 PWM mode......................................... 191 Reset-synchronized PWM mode ........ 203 Synchronous operation ....................... 183 Operating modes....................................... 39 Pin function controller ............................ 433 Pin functions in each operating mode. 433 The functions of multiplexed pins ...... 433 Power-down modes ................................ 493 Module standby mode......................... 504 Sleep mode ......................................... 501 Software standby mode....................... 501 Processing states ....................................... 37 Exception processing state.................... 38 Power-down state.................................. 38 Program execution state........................ 38 Reset state ............................................. 38 RAM ....................................................... 491 Registers ADCR ......................... 374, 537, 547, 555 ADCSR....................... 373, 537, 547, 554 ADDR................................................. 372 ADTSR ....................... 376, 539, 548, 555 BCR1 .......................... 131, 538, 548, 555 BRR ............................ 327, 531, 541, 551 CMCNT ...................... 390, 536, 546, 554 CMCOR...................... 390, 536, 546, 554 CMCSR ...................... 389, 536, 546, 554 CMSTR....................... 388, 536, 546, 554 DTBR.......................... 113, 538, 548, 555 DTCRA............................................... 110 DTCRB............................................... 110 DTCSR ....................... 112, 538, 548, 555 DTDAR .............................................. 110 DTE .................................... 538, 548, 555 DTER.................................................. 111 Rev. 4.00 Dec 05, 2005 page 562 of 564 REJ09B0270-0400 DTIAR ................................................ 110 DTMR ................................................. 108 DTSAR ............................................... 110 EBR1........................... 467, 537, 547, 555 EBR2........................... 468, 537, 547, 555 FLMCR1 ..................... 465, 537, 547, 555 FLMCR2 ..................... 467, 537, 547, 555 ICR1.............................. 70, 534, 544, 553 ICR2.............................. 71, 534, 544, 553 ICSR1.......................... 295, 536, 545, 554 ICSR2.......................... 427, 536, 545, 554 IPR ................................ 74, 534, 544, 553 ISR ................................ 73, 534, 544, 553 MMT_TCNT............... 405, 539, 548, 556 MMT_TDDR .............. 405, 539, 548, 556 MMT_TMDR ............. 401, 539, 548, 556 MMT_TSR.................. 404, 539, 548, 556 MSTCR ....................... 499, 538, 548, 555 OCSR .......................... 298, 536, 545, 554 PACRL........................ 439, 535, 544, 553 PADRL ....................... 450, 535, 544, 553 PAIORL ...................... 439, 535, 544, 553 PBCR .......................... 443, 535, 545, 553 PBDR .......................... 452, 535, 545, 553 PBIOR......................... 442, 535, 545, 553 PDDRL ............................................... 535 PDIORL .............................................. 535 PECRH........................ 445, 535, 545, 554 PECRL ........................ 445, 535, 545, 554 PEDRH ....................... 454, 535, 545, 554 PEDRL........................ 454, 535, 545, 553 PEIORH ...................... 444, 535, 545, 554 PEIORL....................... 444, 535, 545, 554 PFDR........................... 456, 535, 545, 553 PGDR.......................... 458, 536, 545, 554 RAMER .............. 131, 469, 538, 548, 555 RDR ............................ 320, 531, 541, 551 RSR..................................................... 320 RSTCSR...................... 308, 538, 547, 555 SBYCR ....................... 496, 538, 548, 555 Index SCR............................. 322, 531, 541, 551 SDCR.......................... 327, 531, 541, 551 SMR............................ 321, 531, 541, 551 SSR ............................. 324, 531, 541, 551 SYSCR........................ 498, 538, 548, 555 TBR............................. 405, 539, 549, 556 TCBR.......................... 177, 532, 542, 552 TCDR.......................... 176, 532, 542, 551 TCNR.......................... 402, 539, 548, 556 TCNT......... 169, 305, 532, 538, 541, 547, 551, 555 TCNTS........................ 176, 532, 542, 552 TCR............................. 140, 532, 541, 551 TCSR .......................... 305, 538, 547, 555 TDCNT ....................... 405, 539, 549, 556 TDDR ......................... 176, 532, 542, 551 TDR ............................ 320, 531, 541, 551 TGCR.......................... 174, 532, 541, 551 TGR ............................ 169, 405, 532, 539 TIER ........................... 164, 532, 541, 551 TIOR ........................... 146, 532, 541, 551 TMDR......................... 144, 532, 541, 551 TOCR.......................... 173, 532, 541, 551 TOER.......................... 172, 532, 541, 551 TPBR .......................... 406, 539, 548, 556 TPDR .......................... 406, 539, 548, 556 TSR ..................... 166, 320, 532, 542, 552 TSTR........................... 170, 533, 542, 552 TSYR .......................... 170, 533, 542, 552 UBAMR ........................ 93, 537, 547, 555 UBAR ........................... 93, 537, 547, 555 UBBR............................ 94, 537, 547, 555 UBCR............................ 96, 537, 547, 555 RISC..........................................................14 Serial communication interface...............317 Asynchronous serial communication ..340 Clocked synchronous communication 357 System registers ........................................12 Multiply-and-Accumulate Registers (MAC)...................................................12 Procedure Register (PR)........................12 Program Counter (PC)...........................12 User break controller.................................91 Watchdog timer.......................................303 Interval Timer Mode ...........................311 Reading from TCNT, TCSR, and RSTCSR..............................................314 Watchdog Timer Mode .......................309 Writing to RSTCSR ............................314 Writing to TCNT and TCSR ...............313 Rev. 4.00 Dec 05, 2005 page 563 of 564 REJ09B0270-0400 Index Rev. 4.00 Dec 05, 2005 page 564 of 564 REJ09B0270-0400 Renesas 32-Bit RISC Microcomputer Hardware Manual SH7046 Group Publication Date: 1st Edition, March 2001 Rev.4.00, December 05, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. (c)2005. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 205, AZIA Center, No.133 Yincheng Rd (n), Pudong District, Shanghai 200120, China Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 5.0 SH7046 Group Hardware Manual |
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